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lithium ion battery monitoring system ad7280a rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features 12-bit adc, 1 s per channel conversion time 6 analog input channels, common-mode range 0.5 v to 27.5 v 6 auxiliary adc inputs 1.6 mv cell voltage accuracy on-chip voltage regulator cell balancing interface daisy-chain interface internal reference: 3 ppm/ o c 1.8 a power-down current high input impedance serial interface with alert function 1 spi interface for up to 48 channels crc protection on read and write commands on-chip registers for channel sequencing v dd operating range: 8 v to 30 v temperature range: ?40c to +105c 48-lead lqfp qualified for automotive applications applications lithium ion battery monitoring electric and hybrid electric vehicles power supply backup power tools functional block diagram clock 2.5v ref regulator cell balancing interface daisy-chain interface ad7280a 12-bit adc v dd v reg dgnd dv cc v ss agnd sdolo alertlo av cc v drive sclk sdi sdo alert cs pd cnvst master refgnd c ref v ref aux term lv mux aux6 aux5 aux4 aux3 aux2 aux1 hv mux vin6 vin5 vin4 vin3 vin2 vin1 vin0 sclkhi sdihi sdohi alerthi cshi pdhi cnvsthi cb1 cb2 cb3 cb4 cb5 cb6 limit reg sqn logic data memory spi interface control logic and self-test 09435-001 figure 1. general description the ad7280a 1 contains all the functions required for general- purpose monitoring of stacked lithium ion batteries as used in hybrid electric vehicles, battery backup applications, and power tools. the part has multiplexed cell voltage and auxiliary adc measurement channels for up to six cells of battery management. an internal 3 ppm/c reference is provided that allows a cell voltage accuracy of 1.6 mv. the adc resolution is 12 bits and allows conversion of up to 48 cells within 7 s. the ad7280a operates from a single v dd supply that has a range of 8 v to 30 v (with an absolute maximum rating of 33 v). the part provides six differential analog input channels to accommodate large common-mode signals across the full v dd range. each channel allows an input signal range, vin(+) ? vin(?), of 1 v to 5 v. the input pins assume a series stack of six cells. in addition, the part includes six auxiliary adc input channels that can be used for temperature measurement or system diagnostics. the ad7280a includes on-chip registers that allow a sequence of channel measurements to be programmed to suit the application requirements. the ad7280a also includes a dynamic alert function that can detect whether the cell voltages or auxiliary adc inputs exceed an upper or lower limit defined by the user. the ad7280a has cell balancing interface outputs designed to control external fet transistors to allow discharging of individual cells. the ad7280a includes a built-in self-test feature that internally applies a known voltage to the adc inputs. a daisy-chain interface allows up to eight parts to be stacked without the need for individual device isolation. the ad7280a requires only one supply pin that accepts 6.9 ma under normal operation while converting at 1 msps. all this functionality is provided in a 48-lead lqfp package operating over a temperature range of ?40c to +105c. 1 patents pending.
ad7280a rev. 0 | page 2 of 48 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? power specifications .................................................................... 5 ? timing specifications .................................................................. 6 ? absolute maximum ratings ............................................................ 7 ? thermal resistance ...................................................................... 7 ? esd caution .................................................................................. 7 ? pin configuration and function descriptions ............................. 8 ? typical performance characteristics ........................................... 11 ? terminology .................................................................................... 14 ? theory of operation ...................................................................... 15 ? circuit information .................................................................... 15 ? converter operation .................................................................. 15 ? analog input structure .............................................................. 16 ? transfer function ....................................................................... 16 ? typical connection diagrams .................................................. 17 ? reference ..................................................................................... 19 ? converting cell voltages and auxiliary adc inputs ........... 19 ? converting cell voltages and auxiliary adc inputs in a chain of ad7280as ............................................................ 21 ? conversion window .................................................................. 22 ? self-test conversion .................................................................. 22 ? connection of fewer than six voltage cells ............................. 22 ? auxiliary adc inputs ................................................................ 23 ? power requirements .................................................................. 23 ? power-down ............................................................................... 24 ? power-up time ........................................................................... 25 ? cell balancing outputs .............................................................. 25 ? alert output ................................................................................ 27 ? register map ................................................................................... 28 ? cell voltage registers ................................................................ 28 ? auxiliary adc registers ........................................................... 28 ? self-test register ........................................................................ 28 ? control register ......................................................................... 28 ? cell overvoltage register .......................................................... 29 ? cell undervoltage register ....................................................... 30 ? aux adc overvoltage register .............................................. 30 ? aux adc undervoltage register ........................................... 30 ? alert register .............................................................................. 30 ? cell balance register ................................................................. 30 ? cbx timer registers .................................................................. 30 ? pd timer register ...................................................................... 31 ? read register .............................................................................. 31 ? cnvst control register ........................................................... 31 ? serial interface ................................................................................ 32 ? writing to the ad7280a ........................................................... 32 ? reading from the ad7280a ..................................................... 33 ? daisy-chain interface .................................................................... 34 ? addressing the ad7280a while reading back conversion or register data .......................................................................... 34 ? initializing the ad7280a .......................................................... 34 ? write acknowledge .................................................................... 35 ? cyclic redundancy check ........................................................ 35 ? examples of interfacing with the ad7280a ............................... 38 ? convert and readback routine ............................................... 38 ? examples ...................................................................................... 38 ? emc guidelines ............................................................................. 44 ? schematic and layout guidelines ............................................ 44 ? operation in a noisy environment ......................................... 44 ? software flowchart .................................................................... 45 ? outline dimensions ....................................................................... 46 ? ordering guide .......................................................................... 46 ? automotive products ................................................................. 46 ? revision history 4/11revision 0: initial version
ad7280a rev. 0 | page 3 of 48 specifications v dd = 8 v to 30 v, v ss = 0 v, dv cc = av cc = v reg , v drive = 2.7 v to 5.5 v, t a = ?40c to +105c, unless otherwise noted. table 1. parameter min typ max unit test conditions/comments dc accuracy (vin0 to vin6) 1 resolution 12 bits no missing codes integral nonlinearity 1 lsb differential nonlinearity 0.8 lsb offset error 1 lsb offset error match 1 lsb gain error 1 lsb gain error match 1 lsb adc unadjusted error 2 , 3 1.2 mv total unadjusted error 4 , 5 9 mv v in range 6 = 1 v to 4.1 v, ?10c to +85c 10 mv v in range 6 = 1 v to 4.1 v, ?40c to +85c 1.6 14.5 mv v in range 6 = 1 v to 4.1 v, ?40c to +105c cell voltage inputs (vin0 to vin6) pseudo differential input voltage vin(x) ? vin(x ? 1) 1 2 v ref v absolute input voltage v cm ? v ref v cm + v ref v common-mode input voltage 0.5 27.5 v static leakage current 7 5 70 na dynamic leakage current 7 3 na cnvst pulse every 100 ms input capacitance 15 pf dc accuracy (aux1 to aux6) 1 , 8 resolution 12 bits no missing codes integral nonlinearity 1 lsb differential nonlinearity 0.8 lsb offset error 2 lsb offset error match 2 lsb gain error 2 lsb gain error match 2 lsb adc unadjusted error 9 1.2 mv total unadjusted error 10 20 mv ?40c to +85c 1.6 22 mv ?40c to +105c auxiliary adc inputs (aux1 to aux6) input voltage range 0 2 v ref v static leakage current 7 15 na dynamic leakage current 7 3 na cnvst pulse every 100 ms input capacitance 15 pf reference reference voltage 2.494 2.5 2.506 v ?40c to +85c 2.494 2.5 2.509 v ?40c to +105c reference voltage temperature coefficient 3 15 ppm/c ?40c to +85c 11 ppm/c ?40c to +105c output voltage hysteresis 50 ppm ?40c to +105c long-term drift 150 ppm/1000 hours line regulation 5 ppm/v turn-on settling time 11 , 12 5.5 10 ms v reg = 1 f, v ref = 1 f, c ref = 100 nf
ad7280a rev. 0 | page 4 of 48 parameter min typ max unit test conditions/comments regulator output (v reg ) input voltage range 8 30 v output voltage, v reg 13 4.9 5.2 5.5 v 5 ma external load output current 14 5 ma line regulation 0.5 mv/v load regulation 2.5 mv/ma internal short protection limit 25 ma for a 10 short cell balancing outputs 15 output high voltage, v oh v reg ? 1 5 v reg + 0.2 v i source = 415 na output low voltage, v ol 0 v cb1 output ramp-up time 16 30 s for an 80 pf load cb1 output ramp-down time 17 30 s for an 80 pf load cb2 to cb6 output ramp-up time 16 380 s for an 80 pf load cb2 to cb6 output ramp-down time 17 30 s for an 80 pf load logic inputs input high voltage, v inh 2.4 v input low voltage, v inl 0.4 v input current, i in 10 a input capacitance, c in 5 pf logic outputs output high voltage, v oh v drive 0.9 v i source = 200 a output low voltage, v ol 0.4 v i sink = 200 a floating state leakage current 10 a floating state output capacitance 5 pf output coding straight binary 1 for dc accuracy specifications, the lsb size for cell voltage measurements is (2 v ref ? 1 v)/4096. the lsb size for auxiliary adc input voltage measurements is (2 v ref )/4096. 2 adc unadjusted error includes the inl of the adc and the ga in and offset errors of the vin0 to vin6 input channels. 3 the conversion accuracy during cell bala ncing is decreased due to the activation of the cell balance ci rcuitry. the adc unadju sted error increases by a factor of 4. 4 total unadjusted error includes the inl of the adc and the gain and offset errors of the vin0 to vin6 input channels, as well as the reference error, that is, the difference between the ideal and actual reference voltage and the te mperature coefficient of the 2.5 v reference. 5 the conversion accuracy during cell bala ncing is decreased due to the activation of the cell balance ci rcuitry. the total unad justed error increases by a factor of 4. 6 for the full analog input range, that is, 1 v to 2 v ref , the total unadjusted error increases by 20%. 7 the total current measured on the input pins while converting is the sum of the static and dynamic leakage currents. see the t erminology section. 8 bit d3 of the control register is set to 0 (thermistor termination resistor function is not in use). 9 adc unadjusted error includes the inl of the adc and the gain and offset errors of the auxx input channels. 10 total unadjusted error includes the inl of the adc and the gain and offset errors of the auxx input channels, as well as the r eference error, that is, the difference between the ideal and actual reference voltage and the temperature coefficient of the 2.5 v reference. 11 the turn-on settling time is the time from the rising edge of the pd signal until the conversion result settles to the specified accuracy. this includes the time required to power up the regulator and the reference. note that a rising edge on the cnvst input is also required to power up the reference. this rising edge should occur after the rising edge on pd . 12 sample tested during initial release to ensure compliance. 13 the regulator output voltage is specified with an external 5 ma load in addition to the current required to drive the av cc , dv cc , and v drive supplies of the ad7280a. 14 this specification refers to the maximum regulator output current that is available for external use. 15 the cbx outputs can be set to 0 v or v reg with respect to the negative terminal of the cell being balanced. 16 the cb1 to cb6 output ramp-up times are defined from the rising edge of the cs command until the cb output exceeds v reg ? 1 v with respect to the negative terminal of the cell being balanced. 17 the cb1 to cb6 output ramp-down times are defined from the rising edge of the cs command until the cb output falls belo w 50 mv with respect to the negative terminal of the cell being balanced.
ad7280a rev. 0 | page 5 of 48 power specifications v dd = 8 v to 30 v, v ss = 0 v, dv cc = av cc = v reg , v drive = 2.7 v to 5.5 v, t a = ?40c to +105c, unless otherwise noted. table 2. parameter min typ max unit test conditions/comments power requirements v dd 8 30 v master device i dd during conversion 5.6 7.3 ma i dd during data readback 5.3 7.0 ma i dd during cell balancing 5.1 6.8 ma i dd software power-down 2.5 2.9 ma i dd full power-down mode 1.8 5 a slave device i dd during conversion 6.9 8.7 ma i dd during data readback 6.5 8.2 ma i dd during cell balancing 6.4 8.0 ma i dd software power-down 3.8 4.2 ma i dd full power-down mode 1.8 5 a power dissipation master device v dd = 30 v during conversion 170 220 mw during data readback 160 210 mw during cell balancing 155 205 mw software power-down 75 90 mw full power-down mode 54 150 w slave device v dd = 30 v during conversion 210 265 mw during data readback 195 250 mw during cell balancing 192 240 mw software power-down 115 130 mw full power-down mode 54 150 w
ad7280a rev. 0 | page 6 of 48 timing specifications v dd = 8 v to 30 v, v ss = 0 v, dv cc = av cc = v reg , v drive = 2.7 v to 5.5 v, t a = ?40c to +105c, unless otherwise noted. table 3. parameter 1 min typ max unit description t conv adc conversion time 425 560 695 ns ?40c to +85c 425 720 ns ?40c to +105c t acq adc acquisition time, bits[d6:d5] of the control register set to 00 340 400 465 ns ?40c to +85c 340 470 ns ?40c to +105c t acq adc acquisition time, bits[d6:d5] of the control register set to 01 665 800 1010 ns ?40c to +85c 665 1030 ns ?40c to +105c t acq adc acquisition time, bits[d6:d5] of the control register set to 10 1005 1200 1460 ns ?40c to +85c 1005 1510 ns ?40c to +105c t acq adc acquisition time, bits[d6:d5] of the control register set to 11 1340 1600 1890 ns ?40c to +85c 1340 1945 ns ?40c to +105c t delay 200 250 ns propagation delay between the falling edges of cnvst of adjacent parts in the daisy chain t wait 5 s time required between the end of conversions and the beginning of readback of the conversion results f sclk 1 mhz frequency of serial read clock t quiet 200 ns minimum quiet time required between the end of a serial read and the start of the next conversion t 1 2 0.4 50 s cnvst low pulse t 2 10 ns cs falling edge to sclk rising edge t 3 20 ns delay from cs falling edge until sdo is three-state disabled t 4 5 ns sdi setup time prior to sclk falling edge t 5 4 ns sdi hold time after sclk falling edge t 6 3 28 ns data access time after sclk rising edge t 7 20 ns sclk to data valid hold time t 8 0.45 t sclk ns sclk high pulse width t 9 0.45 t sclk ns sclk low pulse width t 10 4 100 ns cs rising edge to sclk rising edge t 11 10 ns cs rising edge to sdo high impedance t 12 3 s cs high time required between each 32-bit write/read command 1 sample tested during initial release to ensure compliance. all input signals are specified with t r = t f = 5 ns (10% to 90% of v drive ) and timed from a voltage level of 1.6 v. all timing specifications given are with a 25 pf load capacitance. 2 maximum allowed cnvst low pulse time to ensure that a software power-down state is not entered when the cnvst pin is not gated. 3 time required for the output to cross 0.4 v or 2.4 v. 4 t 10 applies when using a continuou s sclk. guaranteed by design. timing diagram 0 9435-020 t 8 t 10 three-state three-state s clk sdo sdi lsb msb msb ? 1 msb msb ? 1 32 4 3 2 1 lsb t 12 t 2 3 t 6 t t 7 t 4 t 5 t 11 t 9 cs figure 2. serial interface timing diagram
ad7280a rev. 0 | page 7 of 48 absolute maximum ratings t a = 25c, unless otherwise noted. table 4. parameter rating v dd to v ss , agnd ?0.3 v to +33 v v ss to agnd, dgnd ?0.3 v to +0.3 v vin0 to vin5 voltage to v ss , agnd v ss ? 0.3 v to v dd + 0.3 v vin6 voltage to v ss , agnd v dd ? 0.3 v to v dd + 1 v cb1 output to v ss , agnd ?0.3 v to dv cc + 0.3 v cbx output to vin(x ? 1) 1 ?0.3 v to vin(x ? 1) 1 + 7 v aux1 to aux6 voltage to v ss , agnd ?0.3 v to av cc + 0.3 v aux term voltage to v ss , agnd ?0.3 v to av cc + 0.3 v av cc to v ss , agnd, dgnd ?0.3 v to +7 v dv cc to av cc ?0.3 v to +0.3 v dv cc to v ss , dgnd ?0.3 v to +7 v v drive to v ss , agnd ?0.3 v to +7 v agnd to dgnd ?0.3 v to +0.3 v digital input voltage to v ss , dgnd ?0.3 v to v drive + 0.3 v digital output voltage to v ss , dgnd ?0.3 v to v drive + 0.3 v input current to any pin except supply pins 2 10 ma operating temperature range ?40c to +105c storage temperature range ?65c to +150c junction temperature 150c pb-free temperature, soldering reflow 260(+0)c esd 2 kv 1 x = 2 to 6. 2 transient currents of up to 100 ma do not cause scr latch-up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. to conform with ipc 2221 industrial standards, it is advisable to use conformal coating on the high voltage pins. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 5. thermal resistance package type ja jc unit 48-lead lqfp (st-48) 76.2 17 c/w esd caution
ad7280a rev. 0 | page 8 of 48 pin configuration and fu nction descriptions 48 pdhi 47 cshi 46 sclkhi 45 sdohi 44 cnvsthi 43 sdihi 42 alerthi 41 refgnd 40 v ref 39 c ref 38 aux1 37 aux2 35 aux4 34 aux5 33 aux6 30 av cc 31 agnd 32 aux term 36 aux3 29 v drive 28 alertlo 27 alert 25 sdolo 26 sdo 2 cb6 3 v in5 4 cb5 7 v in3 6 cb4 5 v in4 1 v in6 8 cb3 9 v in2 10 cb2 12 cb1 11 v in1 13 vin0 14 master 15 pd 16 v dd 17 v ss 18 v reg 19 dv cc 20 dgnd 21 cs 22 sclk 23 sdi 24 cnvst pin 1 ad7280a top view (not to scale) 09435-003 figure 3. pin configuration table 6. pin function descriptions pin no. mnemonic description 1, 3, 5, 7, 9, 11, 13 vin6 to vin0 analog input 6 to analog input 0. vin0 should be connec ted to the base of the series-connected battery cells. vin1 should be connected to the top of cell 1, vin2 sh ould be connected to the top of cell 2, and so on (see figure 28 and figure 29 ). 2, 4, 6, 8, 10, 12 cb6 to cb1 cell balance output 6 to cell balance output 1. these pins provide a voltage output that can be used to supply the gate drive of an external cell balancing transist or. each cbx output provides a 0 v or 5 v voltage output referenced to the absolute amplitude of the negative terminal of the battery cell that is being balanced. 14 master voltage input. connect the master pin of the ad7280a that is connected directly to the dsp/microprocessor to the v dd supply pin through a 10 k resistor. in an applic ation with two or more ad7280as in a daisy chain, the master pins of the remaining ad7280as in the da isy chain should be tied to their respective v ss supply pins through 10 k resistors. 15 pd power-down input. this input is used to power do wn the ad7280a. when the ad7280a acts as a master, the pd input is supplied from the dsp/microprocessor. when the ad7280a acts as a slave in a daisy chain, the pd input should be connected to the pdhi output of the ad7280a immediately below it in potential in the daisy chain. 16 v dd positive power supply voltage for the high voltage analog input structure of the ad7280a. the supply must be greater than the minimum voltage of 8 v. v dd can be supplied directly from the cell with the highest potential of the four, five, or six cell battery stacks that the ad7280a is monitoring. the maximum voltage that should be applied between v dd and v ss is 30 v. place 10 f and 100 nf decoupling capacitors on the v dd pin. 17 v ss negative power supply voltage for the high voltage anal og input structure of the ad7280a. this input should be at the same potential as the agnd/dgnd voltage. 18 v reg analog voltage output, 5.2 v. the internally generated v reg voltage, which provides the supply voltage for the adc core, is available on this pin for use exte rnal to the ad7280a. place 1 f and 100 nf decoupling capacitors on the v reg pin. 19 dv cc digital supply voltage, 4.9 v to 5.5 v. the dv cc and av cc voltages should ideally be at the same potential. for best performance, it is recommended that the dv cc and av cc pins be shorted together to ensure that the voltage difference between them never exceeds 0.3 v, even on a transient basis. this supply should be decoupled to dgnd. place 100 nf decoupling capacitors on the dv cc pin. the dv cc supply pin should be connected to the v reg output. 20 dgnd digital ground. ground reference point for all digital circuitry on the ad7280a. the dgnd and agnd voltages should ideally be at the same potential and must not be more than 0.3 v apart, even on a transient basis.
ad7280a rev. 0 | page 9 of 48 pin no. mnemonic description 21 cs chip select input. the cs input is used to frame the input and output data on the spi and daisy-chain interfaces. on the master ad7280a device, the cs input is supplied from the dsp/microprocessor. when the ad7280a acts as a slave in a daisy chain, this input should be connected to the cshi output of the ad7280a immediately below it in pot ential in the daisy chain. 22 sclk serial clock input. on the master ad7280a device, the sclk input is supplied from the dsp/microprocessor. when the ad7280a acts as a slave in a daisy chain, this input should be connected to the sclkhi output of the ad7280a immediately below it in potential in the daisy chain. 23 sdi serial data input. data to be written to the on-chip regi sters is provided on this in put and is clocked into the ad7280a on the falling edge of the sclk input. on th e master ad7280a device, sdi is the data input of the spi interface. when the ad7280a acts as a slave in a daisy chain, this input a ccepts data from the sdohi output of the ad7280a immediately below it in potential in the daisy chain. 24 cnvst convert start input. the conversion is initiated on the falling edge of cnvst . on the master ad7280a, the cnvst pulse is supplied from the dsp/microproces sor; this input can also be tied to dv cc and the conversion initiated through the serial interface. when the ad7280a ac ts as a slave in a daisy chain, this input should be connected to the cnvsthi output of the ad7280a immediately below it in potential in the daisy chain. 25 sdolo serial data output in daisy-chain mode. on the mast er ad7280a device, this output should be connected to v ss either directly or through a pull-down, 1 k resistor . when the ad7280a acts as a slave in a daisy chain, this output should be connected to the sdihi input of the ad7280a immediately below it in potential in the daisy chain. 26 sdo serial data output. the conversion outp ut data or the register output data is supplied to this pin as a serial data stream. the bits are clocked out on the rising edge of the sclk input; 32 sclks are required to access the data. on the master ad7280a device, the sdo outp ut should be connected to the dsp/microprocessor. the sdo outputs of the remaining ad7280as in the daisy chain should be connected to v ss either directly or through a pull-down, 1 k resistor. 27 alert digital output. this flag indicates ce ll or auxiliary adc input overvoltage or undervoltage. the alert output of the master ad7280a should be connected to the dsp/ microprocessor. the alert o utputs of the remaining ad7280as in the daisy chain should be connected to v ss either directly or through a pull-down, 1 k resistor. 28 alertlo alert output in daisy-chain mode. on the master ad7280a, this output should be connected to v ss either directly or through a pull-down, 1 k resistor. when the ad7280a acts as a slave in a daisy chain, this output should be connected to the alerthi input of the ad7280a immediately below it in potential in the daisy chain. 29 v drive logic power supply input. the voltage supplied at this pin determines the voltage at which the spi interface operates. this pin should be decoupled to dgnd. on the master ad7280a device, the voltage range on this pin is 2.7 v to 5.5 v. the v drive voltage can be different from the voltage at av cc and dv cc , but it should never exceed either by more than 0.3 v. the v drive pin of the remaining ad7280as in the daisy chain should be connected to v reg . 30 av cc analog supply voltage for the adc core, 4.9 v to 5.5 v. the av cc and dv cc voltages should ideally be at the same potential. for best performance, it is recommended that the av cc and dv cc pins be shorted together to ensure that the voltage difference between them never exceeds 0.3 v, even on a transient basis. this supply should be decoupled to agnd. place 100 nf decoupling capacitors on the av cc pin. the av cc supply pin should be connected to the v reg output. 31 agnd analog ground. this pin is the ground reference point fo r all analog circuitry on th e ad7280a. this input should be at the same potential as the base of the series-connected battery cells. the agnd and dgnd voltages should ideally be at the same potential and must not be more than 0.3 v apart, even on a transient basis. 32 aux term thermistor termination resistor input. if this function is not required in the appl ication, it is recommended that this pin be connected to v reg through a 10 k resistor. 33 to 38 aux6 to aux1 auxiliary, single-ended 5 v adc inputs. if any of thes e inputs is not required in the application, it is recommended that the pin be connected to v reg through a 10 k resistor. 39 c ref reference capacitor. a 100 nf decoupling capacito r to refgnd should be placed on this pin. 40 v ref reference output, 2.5 v. the on-chip reference is available on this pin for use external to the ad7280a. a 1 f decoupling capacitor to refgnd is recommended on this pin. 41 refgnd reference ground. this pin is the ground reference point for the internal band gap reference circuitry on the ad7280a. the refgnd voltage should be at the same potential as the agnd voltage. 42 alerthi alert input in daisy-chain mode. the alert signal from each ad7280a in the daisy chain is passed through the alertlo output and the alerthi input of each ad7280a in the chain and is supplied to the dsp/micro- processor through the alert output of the master ad7280a . this input should be connected to the alertlo output of the ad7280a immediately above it in potential in the daisy chain. the ad7280a at the highest potential in the stack does not require an alert inp ut; in this case, the pin should be connected to v dd through a 1 k resistor.
ad7280a rev. 0 | page 10 of 48 pin no. mnemonic description 43 sdihi serial data input in daisy-chain mode . the data from each ad7280a in th e daisy chain is passed through the sdolo output and the sdihi input of each ad7280a in the chain and is supplied to the dsp/microprocessor through the sdo output of the master ad7280a. this inp ut should be connected to the sdolo output of the ad7280a immediately above it in potenti al in the daisy chain. the ad7280a at the highest potential in the stack does not require a serial data input in daisy-chai n mode; in this case, the pin should be connected to v dd through a 1 k resistor. 44 cnvsthi conversion start output in daisy-chain mode. the convert start signal from the dsp/microprocessor supplied to the cnvst input of the master ad7280a is passed through each ad7280a by means of the cnvst input and the cnvsthi output. this output should be connected to the cnvst pin of the ad7280a immediately above it in potential in the daisy chain. the ad7280a at the highest potential in the stack does not require a daisy-chain conversion start output; in th is case, the pin should be connected to v dd . 45 sdohi serial data output in dais y-chain mode. the serial data input from the dsp/microprocessor supplied to the sdi input of the master ad7280a is passed through ea ch ad7280a by means of the sdi input and the sdohi output. this output should be conne cted to the sdi input of the ad7280a immediately above it in potential in the daisy chain. the ad7280a at the highest potentia l in the stack does not require a daisy-chain serial data output; in this case, the pin should be connected to v dd . 46 sclkhi serial clock output in daisy-chain mode. the clock si gnal from the dsp/microprocessor supplied to the sclk input of the master ad7280a is passed through each ad7280a by means of the sclk input and the sclkhi output. this output should be connected to th e sclk input of the ad7280a immediately above it in potential in the daisy chain. the ad 7280a at the highest potential in the stack does not require a daisy-chain serial clock output; in this case, the pin should be connected to v dd . 47 cshi chip select output in daisy-chain mode. the chip select signal from the dsp/microprocessor supplied to the cs input of the master ad7280a is passed through each ad7280a by means of the cs input and the cshi output. this output should be connected to the cs input of the ad7280a immediat ely above it in potential in the daisy chain. the ad7280a at the highest potentia l in the stack does not require a daisy-chain chip select output; in this case, the pin should be connected to v dd . 48 pdhi power-down output in daisy-chain mode. the power-d own signal from the dsp/microprocessor supplied to the pd input of the master ad7280a is passed through each ad7280a by means of the pd input and the pdhi output. this output should be connected to the pd input of the ad7280a immediately above it in potential in the daisy chain. the ad 7280a at the highest potential in the stack does not require a daisy-chain power-down output; in this case, the pin should be connected to v dd .
ad7280a rev. 0 | page 11 of 48 typical performance characteristics 5.5 4.9 5.0 5.1 5.2 5.3 5.4 ?40 ?20 0 20 40 60 80 100 v reg voltage (v) temperature (c) v dd = 8v v dd = 10v v dd = 22.5v v dd = 29.9v 09435-102 8 1 2 4 3 5 6 7 ?40 ?20 0 20 40 60 80 100 i dd (ma) temperature (c) slave currents master currents 09435-105 master, v dd = 8v master, v dd = 10v master, v dd = 29.9v slave, v dd = 8v slave, v dd = 10v slave, v dd = 29.9v figure 4. v reg vs. temperature for diffe rent supply voltages, v reg connected to av cc and dv cc figure 7. i dd during cell balancing vs. temperature for different supply voltages 5.5 4.9 5.0 5.1 5.2 5.3 5.4 ?40 ?20 0 20 40 60 80 100 v reg voltage (v) temperature (c) v dd = 8v v dd = 10v v dd = 22.5v v dd = 29.9v 09435-103 8 1 2 4 3 5 6 7 ?40 ?20 0 20 40 60 80 100 i dd (ma) temperature (c) slave currents master currents 09435-106 master, v dd = 8v master, v dd = 10v master, v dd = 29.9v slave, v dd = 8v slave, v dd = 10v slave, v dd = 29.9v figure 5. v reg vs. temperature for diffe rent supply voltages, v reg connected to av cc and dv cc , 5 ma external load figure 8. i dd during software power-down vs. temperature for different supply voltages 8 1 2 4 3 5 6 7 ?40 ?20 0 20 40 60 80 100 i dd (ma) temperature (c) slave currents master currents 09435-104 master, v dd = 8v master, v dd = 10v master, v dd = 29.9v slave, v dd = 8v slave, v dd = 10v slave, v dd = 29.9v 10,000 8000 6000 4000 2000 0 2668 2667 2666 2665 2664 9149 2663 2662 386 460 5 2661 2660 number of occurrences code 09435-107 figure 6. i dd during conversion vs. temperature for different supply voltages figure 9. histogram of codes for 10,000 samples, odd cell voltage channels
ad7280a rev. 0 | page 12 of 48 2668 2667 2666 2665 2664 2663 2662 2661 2660 code 10,000 8000 6000 4000 2000 0 8870 167 956 7 number of occurrences 09435-108 figure 10. histogram of codes for 10,000 samples, even cell voltage channels 10,000 8000 6000 4000 2000 0 29522951295029492948 236 2947 9072 2946 692 2945 2943 2944 2942 number of occurrences code 09435-109 figure 11. histogram of codes for 10,000 samples, auxiliary channels ?40 ?20 0 20 40 60 80 100 v ref voltage (v) temperature (c) 09435-212 2.496 2.497 2.498 2.499 2.500 2.501 2.502 2.503 2.504 2.505 2.506 2.507 2.508 v dd = 8v v dd = 10v v dd = 16.8v v dd = 22.5v v dd = 29.9v figure 12. v ref vs. temperature for different supply voltages 2.496 2.498 2.500 2.502 2.504 2.506 2.508 ?40 ?20 0 20 40 60 80 100 v ref voltage (v) temperature (c) part 1 part 4 part 7 part 10 part 2 part 5 part 8 part 11 part 3 part 6 part 9 part 12 09435-111 figure 13. v ref vs. temperature for different parts ?40 ?20 0 20 40 60 80 100 total unadjusted error (mv) temperature (c) 09435-214 ?4.5 ?3.0 ?1.5 0 1.5 3.0 4.5 6.0 7.5 v dd = 8v v dd = 10v v dd = 16.8v v dd = 22.5v v dd = 29.9v figure 14. total unadjusted error for even cell voltage channels (absolute value) vs. temperature for different supply voltages ?40 ?20 0 20 40 60 80 100 total unadjusted error (mv) temperature (c) 09435-215 ?4.5 ?3.0 ?1.5 0 1.5 3.0 4.5 6.0 7.5 v dd = 8v v dd = 10v v dd = 16.8v v dd = 22.5v v dd = 29.9v figure 15. total unadjusted error for odd cell voltage channels (absolute value) vs. temperature for different supply voltages
ad7280a rev. 0 | page 13 of 48 ?40 ?20 0 20 40 60 80 100 total unadjusted error (mv) temperature (c) 09435-216 ?4.5 ?3.0 ?1.5 0 1.5 3.0 4.5 6.0 7.5 v dd = 8v v dd = 10v v dd = 16.8v v dd = 22.5v v dd = 29.9v 0 5 4 3 2 1 024681 voltage (v) time (ms) 0 pd v reg v ref 09435-117 figure 16. total unadjusted error for auxiliary channels (absolute value) vs. temperature for different supply voltages figure 19. power-up time, 10 f capacitor on the v ref and v reg pins 0 5 4 3 2 1 024681 voltage (v) time (ms) 0 pd v reg v ref 09435-115 0 5 4 3 2 1 024681 voltage (v) time (ms) 0 pd v reg v ref 09435-118 figure 17. power-up time, 1 f capacitor on the v ref and v reg pins figure 20. power-down time, 10 f capacitor on the v ref and v reg pins 3.2 5.2 4.8 4.4 4.0 3.6 08 700 600 500 400 300 200 100 cbx output voltage (v) load current (na) 0 5 4 3 2 1 024681 voltage (v) time (ms) 0 pd v reg v ref 09435-116 0 0 09435-119 figure 18. power-down time, 1 f capacitor on the v ref and v reg pins figure 21. cbx output voltage vs. load current
ad7280a rev. 0 | page 14 of 48 terminology differential nonlinearity (dnl) dnl is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. integral nonlinearity (inl) inl is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale (a point 1 lsb below the first code transition) and full scale (a point 1 lsb above the last code transition). offset error offset error applies to straight binary output coding. it is the deviation of the first code transition (000 ... 000) to (000 ... 001) from the ideal, that is, agnd + 1 lsb for aux1 to aux6 and 1 v + agnd + 1 lsb for vin0 to vin6. offset error match offset error match is the difference in zero code error across all six channels. gain error gain error applies to straight binary output coding. it is the deviation of the last code transition (111 ... 110) to (111 ... 111) from the ideal (that is, 2 v ref ? 1 lsb) after adjusting for the offset error. gain error match gain error match is the difference in gain error across all six channels. adc unadjusted error adc unadjusted error includes the inl error and the offset and gain errors of the adc and measurement channel. tot a l un a dju s te d e r ror ( t u e ) tue is the maximum deviation of the output code from the ideal. total unadjusted error includes the inl error, the offset and gain errors, and the reference errors. reference errors include the difference between the actual and ideal reference voltage (that is, 2.5 v) and the reference voltage temperature coefficient. reference voltage temperature coefficient the reference voltage temperature coefficient is derived from the maximum and minimum reference output voltage (v ref ) measured between t min and t max . it is expressed in ppm/c using the following equation: 6 10 ) (v5.2 )()( c)(ppm/ ? ? ? ? ? ? ? ? ? ? = min max ref ref ref tt minvmaxv tcv where: v ref ( max ) is the maximum v ref between t min and t max . v ref ( min ) is the minimum v ref between t min and t max . t max = +85c or +105c. t min = ?40c. output voltage hysteresis output voltage hysteresis, or thermal hysteresis, is defined as the absolute maximum change of reference output voltage after the device is cycled through temperature from either t_hys+ or t_hys?, where: t_hys+ = +25c to t max to +25c t_hys? = +25c to t min to +25c output voltage hysteresis is expressed in ppm using the follow- ing equation: 6 10 c)25( )(c)25( (ppm) ? ? ? ? ? ? ? ? ? = ref ref ref hys v t_hys v v v where: v ref (25c) = v ref at 25c. v ref (t_hys) is the maximum change of v ref at t_hys+ or t_hys?. static leakage current static leakage current is the current measured on the cell voltage and/or the auxiliary adc inputs when the device is static, that is, not converting. dynamic leakage current dynamic leakage current is the current measured on the cell voltage and/or the auxiliary adc inputs when the device is converting, with the static leakage current subtracted. dynamic leakage current is specified with a convert start pulse frequency of 10 hz, that is, every 100 ms. the dynamic leakage current for a different conversion rate can be calculated using the following equation: ? ? ? ? ? ? ? ? = )( )( acnvst bcnvst dyn(a) dyn(b) f fi i where: i dyn(a) is the dynamic leakage current at the convert start frequency, f cnvst(a) (see tabl e 1 ). i dyn(b) is the dynamic leakage current at the desired convert start frequency, f cnvst(b) .
ad7280a rev. 0 | page 15 of 48 theory of operation circuit information the ad7280a is a lithium ion (li-ion) battery monitoring chip that can monitor the voltage and temperature of four, five, or six series-connected li-ion battery cells. the ad7280a also provides an interface that can be used to control external transistors for cell balancing. the v dd and v ss supplies required by the ad7280a should be taken from battery cells being monitored by the part. an internal v reg rail is generated to provide power for the adc and the internal interface circuitry. this v reg voltage is available on an output pin for use external to the ad7280a. the ad7280a consists of a high voltage input multiplexer, a low voltage input multiplexer, and a sar adc. the high voltage multiplexer allows four, five, or six series-connected li-ion battery cells to be measured. the low voltage multiplexer provides the user with six single-ended adc inputs that can be used in combination with external thermistors to measure the tempera- ture of each battery cell. the auxiliary adc inputs can also be used for external diagnostics in the application. initiating conver- sions on all 12 channels, that is, the six cell voltage channels and the six auxiliary adc channels, requires only a single cnvst pulse. alternatively, the conversion can be initiated through the rising edge of cs . each conversion result is stored in an individual result register (see ). table 13 each individual cell voltage and auxiliary adc measurement requires a minimum of 1 s to acquire and complete a conver- sion. depending on the external components connected to the analog inputs of the ad7280a, additional acquisition time may be required. a higher acquisition time can be selected through the control register. the ad7280a also provides a conversion averaging option that can be selected through the control register. this option allows the user to complete two, four, or eight averages on each cell voltage and auxiliary adc measurement. the aver- aged conversion results are stored in the result registers. on power-up, the default combined acquisition and conversion time is 1 s, with the averaging register set to 0, that is, a single conversion per channel. the results of the cell voltage and auxiliary adc conversions are read back via the 4-wire serial peripheral interface (spi). the spi is also used to write to and read from the internal registers. the ad7280a features an alert function that can be triggered if the voltage conversion results or the auxiliary adc conversion results exceed the maximum and minimum voltage thresholds selected by the user. the alert modes and threshold levels are selected by writing to internal registers. the ad7280a provides six analog output voltages that can be used to control external transistors as part of a cell balancing circuit. each cell balance output provides a 0 v or 5 v voltage, with respect to the potential on the base of each individual cell, that can be applied to the gate of the external cell balancing transistors. the ad7280a features a daisy-chain interface. individual ad7280a devices can monitor the cell voltages and tempera- tures of six cells. a chain of ad7280as can be used to monitor the cell voltages and temperatures of a larger number of cells. the conversion data from each ad7280a in the chain passes to the system controller via a single spi interface. control data can similarly be passed via the spi up the chain to each individual ad7280a. the ad7280a includes an on-chip 2.5 v reference. the reference voltage is available for use external to the ad7280a. the ad7280a also has a v drive feature to control the voltage at which the serial interface operates. v drive allows the adc to easily interface to both 3 v and 5 v processors. for example, in the recommended configuration, the ad7280a is operated with a supply of 5 v; however, the v drive pin can be powered from a 3 v supply, allowing a large dynamic range with low voltage digital processors. converter operation the conversion paths of the ad7280a consist of a high voltage input multiplexer or a low voltage input multiplexer and a sar adc. the high voltage multiplexer selects the pair of analog inputs, vin0 to vin6, that is to be converted. the voltage of each individual cell is measured by converting the difference between adjacent analog inputs, that is, vin1 ? vin0, vin2 ? vin1, and so on (see figure 22 and figure 23 ). the low voltage multiplexer selects the auxiliary adc input, aux1 to aux6, that is to be converted. the conversion results for each cell voltage and auxiliary adc input can be accessed t wa i t after the programmed conversion sequence is completed. vin6 vin5 vin4 vin3 vin2 vin1 vin0 adc v in+ adc v in? 09435-004 figure 22. mux configuration du ring vin1 to vin0 sampling
ad7280a rev. 0 | page 16 of 48 vin6 vin5 vin4 vin3 vin2 vin1 vin0 adc v in+ adc v in? 09435-005 figure 23. mux configuration du ring vin2 to vin1 sampling the adc is a successive approximation register analog-to- digital converter (sar adc). the converter is composed of a comparator, a sar, control logic, and two capacitive dacs. figure 24 shows a simplified schematic of the converter. during the acquisition phase, the sw1, sw2, and sw3 switches are closed. the sampling capacitor array acquires the signal on the input during this phase. capacitive dac capacitive dac control logic comparator sw3 sw1 sw2 v ref v ref v in+ v in? c s c s b a a b 09435-006 figure 24. adc configuration during acquisition phase when the adc starts a conversion, sw3 opens, and sw1 and sw2 move to position b, causing the comparator to become unbalanced (see figure 25 ). the control logic and capacitive dacs are used to add and subtract fixed amounts of charge to return the comparator to a balanced condition. when the comparator is rebalanced, the conversion is complete. the control logic gen- erates the adc output code. this output code is then stored in the appropriate register for the input that has been converted. capacitive dac capacitive dac control logic comparator sw3 sw1 sw2 v ref v in+ v in? c s c s b a a b v ref 09435-007 figure 25. adc configuration during conversion phase analog input structure figure 26 shows the equivalent circuit of the analog input structure of the ad7280a. the diodes provide esd protection. the resistors are lumped components made up of the on resistance of the input multiplexer, internal track resistance, and other internal switches. the value of these resistors is approximately 300 typical. capacitor c1 is also a lumped component made up of pin capacitance, esd diodes, and switch capacitance, whereas capacitor c2 is the sampling capacitor of the adc. the total lumped capacitance of c1 and c2 is approximately 15 pf. c1 c2 d d r1 v dd v in+ v ss c1 c2 d d r1 v dd v in? v ss 0 9435-008 figure 26. equivalent analog input circuit transfer function the output coding of the ad7280a is straight binary. the designed code transitions occur at successive integer lsb values (that is, 1 lsb, 2 lsbs, and so on). the lsb size is dependent on whether the cell voltage or the auxiliary adc inputs are being measured. the analog input range of the voltage inputs is 1 v to 5 v, and the analog input range of the auxiliary adc inputs is 0 v to 5 v. the ideal transfer characteristic is shown in figure 27 . table 7. lsb sizes for each analog input range selected inputs input range full-scale range lsb size cell voltage 1 v to 5 v 4 v/4096 976 v auxiliary adc inputs 0 v to 5 v 5 v/4096 1.22 mv adc code 111...110 111...000 011...111 000...010 000...001 000...000 111...111 analog input 1v + 1lsb agnd + 1lsb 5v ? 1lsb 5v ? 1lsb 4v input range 5v input range 09435-009 figure 27. ideal transfer characteristic
ad7280a rev. 0 | page 17 of 48 typical connection diagrams vin6 v reg 0.1f 10f 1f 0.1f 0.1f cb6 vin5 cb5 vin4 cb4 vin3 cb3 vin2 cb2 vin1 cb1 vin0 v dd v ss dv cc av cc 1f 0.1f v ref c ref alert cnvst pd sdo sclk sdi cs v drive master ad7280a 10k? 10k ? 10k? 10k? 10k? 10k? 10k? 10k? 10k? 10k? 10k? 10k? 10k? 10k? optional interface pins 4-wire spi interface dsp/micro- processor 09435-010 figure 28. ad7280a configuration diagram for six battery cells the ad7280a can be used to monitor four, five, or six battery cells connected in series. a typical configuration for a six-cell battery monitoring application is shown in figure 28 . however, lithium ion battery applications require a significant number of individual cells to provide the required output voltage. figure 29 shows the recommended configuration of a chain of ad7280as monitoring a larger battery stack. the daisy-chain interface of the ad7280a allows each individual ad7280a to communicate with the ad7280a immediately above and below it. the daisy-chain interface allows the ad7280as to be electrically connected to the battery management chip without the need for individual isolation devices between each ad7280a. as shown in figure 29 , it is recommended that a zener diode be placed across the supplies of each ad7280a. this prevents an overvoltage across the supplies of each ad7280a during the initial connection of the daisy chain of ad7280as to the battery stack. a voltage rating of 30 v is suggested for this zener diode, but lower values can also be used to suit the application. the 10 k resistor in series with the inputs combined with a 100 nf capacitor across the adjacent differential inputs acts as a low-pass filter. the 10 k resistors provide protection for the analog inputs in the event of an overvoltage or undervoltage on those inputs, for example, if any of the cell voltage inputs is incorrectly shorted to v dd or v ss . the resistors also provide protection during the initial connection of the daisy chain of ad7280as to the battery stack. for more information about the daisy-chain interface, see the daisy-chain interface section. in an application that includes a safety mechanism designed to open circuit the battery stack, additional isolation is required between the ad7280a above the break point and the battery management chip. a suggested configuration for the external cell balancing circuit is shown in figure 28 . this configuration also includes 10 k resistors in series with the cell balance outputs. these resistors provide protection for the cell balance outputs in the event of an overvoltage or undervoltage on those inputs. see the cell balancing outputs section for more information.
ad7280a rev. 0 | page 18 of 48 vin6 v dd v ss master pdhi cshi sclkhi sdohi cnvsthi sdihi alerthi v dd pdhi cshi sclkhi sdohi cnvsthi sdihi alerthi pd cs sclk sdi cnvst sdolo alertlo v reg 1f 1f 0.1f 0.1f vin5 vin4 vin3 vin2 vin1 vin0 v ss dv cc av cc alert cnvst pd sdo sclk sdi cs v drive v reg dv cc av cc alert sdo master v ref c ref v drive c ref v ref sdolo alertlo ad7280a ad7280a 10k? 10k? 10k? 1k ? 100nf 100nf 10k? 10k? 100nf 100nf 10k? 10k? ferrite 100nf 10k? 100nf 100nf vin6 vin5 vin4 vin3 vin2 vin1 vin0 10k? 10k? 100nf 10k? 10k? 1k? 1k? 10k? 100nf 100nf 10k? 10k? 100nf 10k? 100nf 100nf 100nf 10f optional interface pins 4-wire spi interface 1f 1f 0.1f 0.1f 22pf 22pf 22pf 22pf 22pf 22pf 22pf 22pf 22pf 22pf 22pf 22pf 22pf 22pf 100nf 100nf 10f v dd 0 100nf 100nf 10f v dd (n ? 1) v dd n v dd 1 v dd 0 v ss 0 v dd 0 v ss v dd pdhi cshi sclkhi sdohi cnvsthi sdihi alerthi pd cs sclk sdi cnvst sdolo alertlo v reg dv cc av cc alert sdo master v ref c ref v drive vin6 vin5 vin4 vin3 vin2 vin1 vin0 10k? 10k? 100nf 10k? 10k? 1k? 1k? 10k? 100nf 100nf 10k? 10k? 100nf 10k? 100nf 100nf 1f 1f 0.1f 0.1f v dd (n ? 1) v dd n 1k ? ad7280a notes all ad7280a devices on the daisy chain should be located on the same pcb. place 22pf daisy-chain capacitors as close as possible to their terminating pins, that is, close to the pin that has the arrow pointing to it on the diagram. route v dd and v ss traces to ensure a low impedance connection between them. route daisy-chain tracks on an inner pcb layer. add a v ss plane from the upper slave device extended down over and under the daisy chain to act as a shield for the daisy chain. place ad7280a parts as close together as possible on the board to minimize the length of the daisy-chain tracks. ferrites on the v dd lines can be replaced with 20 ? resistors except in the case of the v ss 0 connection. in this case, the 20 ? resistor should be replaced with a 0 ? resistor. 1 2 3 4 5 6 7 2 3 4 5 6 7 dsp/micro- processor 09435-011 figure 29. ad7280a daisy-chain configuration
ad7280a rev. 0 | page 19 of 48 reference the internal reference is temperature compensated to 2.5 v. the reference is trimmed to provide a typical drift of 3 ppm/c. as shown in figure 30 , the internal reference circuitry consists of a 1.2 v band gap reference and a reference buffer. the 2.5 v refer- ence is available at the v ref pin. the v ref pin should be decoupled to refgnd using a 1 f or greater ceramic capacitor. the c ref pin should be decoupled to refgnd using a 0.1 f or greater ceramic capacitor. the 2.5 v reference is capable of driving an external load of up to 10 k. v ref refgnd c ref av cc adc self-test voltage band gap 1.2v 09435-012 figure 30. ad7280a internal reference converting cell voltages and auxiliary adc inputs a conversion can be initiated on the ad7280a using either the cnvst input or the serial interface (see the section). a single conversion command initiates conver- sions on all selected channels of the ad7280a. as described in the section, the voltage of each individual battery cell is measured by converting the difference between adjacent analog inputs. the first cell to be converted following a convert start command is cell 6, which is the difference between vin6 and vin5. at the end of the first conversion, the ad7280a generates an internal end-of-conversion (eoc) signal. this internal eoc selects the next cell voltage inputs for measurement through the multiplexer, that is, the difference between vin5 and vin4. the new input is acquired, and a second internal convert start signal is generated, which initiates the conversion. this process is repeated until all the selected voltage and auxiliary adc inputs have been converted. conversion start format converter operation the conversion sequencethat is, the order in which the cell voltages and auxiliary adc inputs are convertedis shown in figure 31 and figure 32 . the cell voltage inputs are converted in reverse order, that is, cell 6 is followed by cell 5, and so on. however, the auxiliary adc inputs are converted in increasing numerical order, that is, aux1 is followed by aux2, and so on. for example, when all 12 inputs are selected for conversion, the conversion of cell 1, that is, vin1 to vin0, is followed by the conversion of the aux1 input. when all selected conversions are completed, the vin6 and vin5 voltage inputs are again selected through the multiplexer, and the voltage across cell 6 is acquired in preparation for the next conversion request. this is the default state for the multiplexer. bits[d15:d14] of the control register select the cell voltage and auxiliary adc inputs to be converted. there are four options available (see table 8 ). table 8. cell voltage and auxiliary adc input selection bits[d15:d14] voltage inputs auxiliary adc inputs 00 6 to 1 1 to 6 01 6 to 1 1, 3, and 5 10 6 to 1 none 11 adc self-test none each voltage and auxiliary adc input conversion requires a minimum of 1 s to acquire and convert the cell voltage or auxiliary adc input voltage. for example, when bits[d15:d14] are set to 00, the falling edge of cnvst triggers a series of 12 conversions. this requires a minimum of 12 s to convert all selected measurements on a single ad7280a. if no auxiliary adc input conversions are required, bits[d15:d14] are set to 10. in this case, the conversion request triggers a series of six conversions, requiring a minimum of 6 s. t 1 t conv t conv t acq volt 6 volt 5 volt 4 aux6 internal ad c conversions cnvst 09435-013 figure 31. adc conversions on the ad7280a t 1 t quiet t wait internal adc conversions serial read operation cnvst volt 6 volt 4 volt 5 volt 6 aux6 volt 5 data readback ? all devices conversion window 09435-014 figure 32. adc conversions and readback on the ad7280a
ad7280a rev. 0 | page 20 of 48 note that 90 s should be allowed before initiating any conver- sions following any change to bits[d15:d14]. this time should be allowed between writing to the control register to change the selected conversions and initiating the first conversion. conversions that are initiated by the rising edge of the cs pin require two separate write commands to the control register. the first command configures the ad7280a for the required acquisition time; the second command, following a delay of 90 s, initiates the conversion on the rising edge of cs . after the completion of all requested conversions, the results can be read back from either a single device or from all devices in a daisy chain by using the spi and daisy-chain interfaces. for more information, see the serial interface section and the daisy-chain interface section. as shown in figure 32 , a wait time, t wa i t , is required between the completion of conversions and the start of readback. this time is required to synchronize the high speed conversion clock and the lower speed clock used for all other ad7280a operations. the minimum value of t wa i t is 5 s. acquisition time the time required to acquire an input signal depends on how quickly the sampling capacitor is charged. this, in turn, depends on the input impedance and any external components placed on the analog inputs. the default acquisition time of the ad7280a on initial power-up is 400 ns. this time can be increased in steps of 400 ns up to 1.6 s to provide flexibility in selecting external components on the analog inputs. the acquisition time is selected by writing to bits[d6:d5] in the control register (see table 9 ). table 9. analog input acquisition time bits[d6:d5] acquisition time 00 400 ns 01 800 ns 10 1.2 s 11 1.6 s the acquisition time required is calculated using the following formula: t acq = 10 (( r source + r ) c ) where: r source should include any extra source impedance on the analog input between the external capacitors (100 nf) and the input pins. it does not include any extra source impedance, for example, the 10 k series resistors, which are between the battery cells and the external capacitors. r is the resistance seen by the track-and-hold amplifier looking at the input, 300 . c is the sampling capacitance, that is, the value of the sampling capacitor, 15 pf. conversion averaging the ad7280a includes an option where the acquisition and conversion of each cell input can be repeated with an averaged conversion result being stored in the individual register. the averaged conversion result can then be read back through the spi interface in the same manner as a standard conversion result. the ad7280a can be programmed, through bits[d10:d9] of the control register, to complete one, two, four, or eight conversions. the default on power-up is a single conversion per channel, that is, no averaging. selection of the two, four, or eight average options through the control register causes the control sequence of both the high voltage and low voltage input multiplexers to be reconfigured to allow the additional acquisitions and conversions to be completed. in each case, the requested number of conversions is completed on each channel before beginning the acquisition and conversion of the next channel in sequence. for example, if an average of two conversions is requested, the new sequence is voltage channel 6, voltage channel 6, voltage channel 5, voltage channel 5, voltage channel 4, and so on. it should also be noted that when the high voltage multiplexer is reconfigured, 90 s should be allowed before initiating any conversions. this time should be allowed between writing to the control register to select averaging and initiating the first conversion. conversions that are being initiated by the rising edge of the cs pin require two separate write commands to the control register. the first command configures the ad7280a for the required averaging, and the second command, after a delay of 90 s, initiates the conversion on the rising edge of cs . suggested external component configuration on analog inputs as described in the acquisition time section, the acquisition time of the ad7280a is selected by the status of bits[d6:d5] in the control register. this provides flexibility in selecting external components on the analog inputs. a suggested configuration for placing external components on the analog inputs to the ad7280a is shown in figure 33 . vin6 vin5 vin4 vin3 vin2 vin1 vin0 ad7280a 10k ? 10k ? 100nf 10k ? 10k ? 100nf 100nf 10k ? 10k ? 100nf 10k ? 100nf 100nf 09435-016 figure 33. external series resistance and shunt capacitance
ad7280a rev. 0 | page 21 of 48 the 10 k resistors in series with the inputs provide protection for the analog inputs in the event of an overvoltage or undervoltage on those inputs. the 100 nf capacitor across the differential inputs acts as a low-pass filter in conjunction with the 10 k resistor. the cutoff frequency of the low-pass filter is 80 hz. using these external components, the default acquisition time of 400 ns can be used, which allows a combined acquisition and conversion time of 1 s. converting cell voltages and auxiliary adc inputs in a chain of ad7280as the ad7280a provides a daisy-chain interface that allows up to eight parts to be stacked without the need for individual isola- tion. one feature of the daisy-chain interface is the ability to initiate conversions on all parts in the daisy-chain stack with a single convert start command. the convert start command is transferred up the daisy chain, from the master device to each ad7280a in turn. the delay time between each ad7280a is t delay , as shown in figure 34 . the maximum delay between the start of conversions on the master ad7280a and the last ad7280a device in the chain can be determined by multiplying t delay by the number of slave ad7280as in the daisy chain. the total conversion time for all cell voltage and auxiliary adc input conversions can be calculated using the following equation: total conversion time = ((t acq + t conv ) (number of conversions per part )) ? t acq + (( n ? 1) t delay ) where: t acq is the analog input acquisition time of the ad7280a (see table 9 ). t conv is the conversion time of the ad7280a, as specified in table 3 . number of conversions per part is the number of inputs selected for conversion (6, 9, or 12, as listed in table 8 ), multiplied by the number of averages selected for each input (1, 2, 4, or 8). n is the number of ad7280as in the daisy chain. t delay is the delay time when transferring the convert start command between adjacent ad7280a devices, as specified in table 3 . the total conversion times calculated for three possible configurations of the ad7280a are included in table 10 . t conv t acq + t conv volt 6 volt 5 total conversion time = (( t acq + t conv ) (#conversions per part)) ? t acq + ((n ? 1) t delay ) volt 4 aux6 t delay t delay t delay t acq + t conv t delay volt 12 volt 11 volt 10 aux12 t acq + t conv volt 18 volt 17 volt 16 aux18 internal ad c conversions part 1 serial read operation part 2 serial read operation part 3 cnvst 09435-015 figure 34. adc conversions and readback on a chain of three ad7280as table 10. calculated conversion times fo r three example ad7280a configurations, t a = ?40c to +85c bits [d15:d14] bits [d10:d9] bits [d6:d5] configuration conversion time per part total conversion time per 48 channel stack 00 00 00 12 channels; t conv = 695 ns; t acq = 465 ns; average = 0 13.46 s 15.2 s 01 12 channels; t conv = 695 ns; t acq = 1.01 s; average = 0 19.45 s 21.2 s 10 12 channels; t conv = 695 ns; t acq = 1.46 s; average = 0 24.4 s 26.15 s 11 12 channels; t conv = 695 ns; t acq = 1.89 s; average = 0 29.13 s 30.9 s 10 00 00 6 channels; t conv = 695 ns; t acq = 465 ns; average = 0 6.5 s 8.23 s 01 6 channels; t conv = 695 ns; t acq = 1.01 s; average = 0 9.22 s 10.97 s 10 6 channels; t conv = 695 ns; t acq = 1.46 s; average = 0 11.47 s 13.22 s 11 6 channels; t conv = 695 ns; t acq = 1.89 s; average = 0 13.62 s 15.37 s 00 11 00 12 channels; t conv = 695 ns; t acq = 465 ns; average = 8 110.9 s 112.65 s 01 12 channels; t conv = 695 ns; t acq = 1.01 s; average = 8 162.67 s 164.42 s 10 12 channels; t conv = 695 ns; t acq = 1.46 s; average = 8 205.42 s 207.17 s 11 12 channels; t conv = 695 ns; t acq = 1.89 s; average = 8 246.27 s 248.02 s
ad7280a rev. 0 | page 22 of 48 conversion window as described in the converting cell voltages and auxiliary adc inputs section, the ad7280a converts the selected cell voltage and auxiliary adc inputs in a defined sequence (see figure 31 ). as described in the circuit information section, the ad7280a consists primarily of a high voltage input multi- plexer, a low voltage input multiplexer, and a sar adc. the six cell voltage channels are presented to the adc in turn by the high voltage multiplexer. control is then handed to the low voltage multiplexer that allows the six auxiliary adc channels to be converted. following completion of all selected conversions, control is handed back to the high voltage multiplexer, and the ad7280a is ready to receive the next valid convert start command. the conversion window of the ad7280a includes the actual con- version time for the selected channels (see tabl e 10 ), as well as the additional time required to return control to the high voltage multiplexer and configure it to start acquiring the cell voltage between vin6 and vin5. the conversion window defines the minimum time that should be allowed between successive convert start commands. the conversion window for the ad7280a can be calculated using the following equation: conversion window = total conversion time + 80 s where total conversion time can be calculated for either a single device or for a chain of devices, as described in the converting cell voltages and auxiliary adc inputs section. self-test conversion a self-test conversion can be initiated on the ad7280a, which allows the operation of the adc and reference buffer to be verified. the self-test conversion is completed on the internal 1.2 v band gap reference voltage, and the voltage range for the conversion is 0 v to 5 v. the self-test conversion can be initi- ated on either a single ad7280a or on all ad7280as in the daisy chain simultaneously. the conversion results can be read back though the read protocols defined in the serial interface section. the self-test conversion result typically varies between code 970 and code 990. the self-test conversion can also be used to verify the operation of the alert outputs, as described in the alert output section. connection of fewer than six voltage cells the ad7280a provides six input channels for battery cell voltage measurement. the ad7280a can also be used in applications that require fewer than six voltage measurements. in these appli- cations, care should be taken to ensure that the sum of the individual cell voltages still exceeds the minimum v dd supply voltage. for this reason, the recommended minimum number of battery cells connected to each ad7280a is 4. care should also be taken to ensure that the voltage on the vin6 input is always greater than or equal to the voltage on the v dd supply pin. for example, in an application with five battery cells connected to the ad7280a, the cell voltage on cell 5 should be applied across vin6 and vin5, and the vin4 and vin5 inputs should be shorted together. figure 35 shows an example of the battery connections to the ad7280a in a four-cell battery monitoring application. vin6 vin5 vin4 vin3 vin2 vin1 vin0 ad7280a 10k ? 10k ? 100nf 10k ? 10k ? 100nf 10k ? 100nf 100nf 09435-017 figure 35. typical connections for a four-cell application regardless of how many cell voltage measurements are required in the user application, the ad7280a acquires and converts the voltages on all six cell voltage input channels. the conversion data on all six voltage channels is supplied to the dsp/microprocessor using the spi/daisy-chain interfaces. users should ignore the conversion data that is not required in their application. it is also possible to read back a single cell voltage conversion result from each device in the daisy chain. this can be done by programming the read register on each device to read back the required conversion result (see example 4 in the examples of interfacing with the ad7280a section). however, as previously described, all six cell voltage channels are converted. when using the device in this mode, the overall conversion sample rate should be limited by the conversion window required for the number of channels selected by bits[d15:d14] of the control register. when using the alert function, the user should program the alert register to ensure that the shorted channels do not incorrectly trigger an alert output (see the alert output section).
ad7280a rev. 0 | page 23 of 48 auxiliary adc inputs the ad7280a provides six single-ended analog inputs to the adcaux1 to aux6which can be used to convert the voltage output of a thermistor temperature measurement circuit. in the event that no temperature measurements are required or that individual cell temperature measurements are not required, the auxiliary adc inputs can be used to convert any other 0 v to 5 v input signal. the ad7280a can be programmed to complete conversions on all six auxiliary adc channels, on three auxiliary adc channels (aux1, aux3, and aux5), or on none of the auxiliary adc input channels. the number of conversions is programmed through bits[d15:d14] of the control register. the number of conversion results supplied by the ad7280a for readback by the dsp/microprocessor is programmed through bits[d13:d12] of the control register. it is also possible to read back a single auxiliary adc conversion result from each device in the daisy chain. this can be done by programming the read register on each device to read back the required conversion result (see example 4 in the examples of interfacing with the ad7280a section). if the device is used in this mode, the overall conversion sample rate should be limited by the conversion window required for the number of channels selected by bits[d15:d14] of the control register. in an application where the alert function is used but only one or two auxiliary adc inputs are required, the ad7280a should first be programmed to complete and read back only three auxiliary adc conversions by setting bits[d15:d12] of the control register to 0101. channel aux5 and channel aux3 can be removed from the alert detection by writing to bits[d1:d0] of the alert register (see table 12 in the alert output section). thermistor termination input if thermistor circuits are used to measure each individual cell temperature, the thermistor termination pin, aux term , can be used to terminate the thermistor inputs for each auxiliary adc input measurement. this reduces the termination resistor requirement from six resistors to one. bit d3 in the control register should be set to 1 when using the aux term input. note that, due to settling time requirements, the thermistor termi- nation resistor option should only be used when the acquisition time of the ad7280a is set to its highest value (1.6 s). the acquisition time is configured by setting bits[d6:d5] of the control register (see table 9 ). in figure 36 , the termination resistor is placed between v ss and aux term . the aux term input can be used to terminate the thermistor inputs to the high or low voltage of the thermistor circuit. v ss aux term r term aux1 aux2 aux3 aux4 aux5 aux6 v reg ad7280a 09435-018 figure 36. typical circuit using the thermistor termination resistor power requirements t he current consumed by the ad7280a in normal operation, that is, when not in power-down mode, is dependent on the mode in which the part is being operated. the three distinct modes of operation can be described as follows: ? voltage and auxiliary adc input conversion ? ad7280a configuration and data readback ? cell balancing the ad7280a consumes its highest level of current while con- verting voltage and/or auxiliary adc inputs to digital outputs. depending on the configuration of the ad7280a, the conversion time can be as little as 6 s. the typical current required by the ad7280a during conversion is 6.9 ma (see table 2 ). when configuring a chain of ad7280as or when reading back the voltage and/or auxiliary adc conversion results from a chain of ad7280as, the current required for each ad7280a is typically 6.5 ma (see table 2 ). the time required to read back the voltage conversions results from 48 lithium ion cells depends on the speed of the interface clock used, that is, sclk, but it can be as low as 1.54 ms. the typical current consumed by the ad7280a when the cell balance outputs are switched on is 6.4 ma (see table 2 ). the length of time for which the cell balance outputs are switched on is defined by the user. when the ad7280a is not being used in any of the aforemen- tioned modes of operation, it is recommended that the device be powered down, as described in the power-down section. this significantly reduces the current drawn by each ad7280a in the chain, which avoids unnecessary draining of the lithium ion cells and aids in current matching between devices across the full battery stack.
ad7280a rev. 0 | page 24 of 48 power-down t he ad7280a provides two power-down options. ? full power-down (hardware) ? software power-down full power-down (hardware) the ad7280a can be placed into full power-down mode, which requires only 5 a maximum current, by taking the pd pin low. the falling edge of the pd pin powers down all analog and digital circuitry. the ad7280a includes a digital delay filter on the pd pin, which protects against a power-down being initiated by noise or glitches on the hardware pd pin. a hardware power-down is not initiated until the pd pin is held low for approximately 130 s. similarly, the ad7280a is not taken out of power-down mode until the pd pin is held high for approximately 130 s. the digital delay filter does not apply on initial power-up. the power-on request is accepted by the ad7280a approximately 5 s after the rising edge of pd . when placing the ad7280a into full power-down mode, av cc and dv cc must fall to 0 v and must not be held high by any external means. av cc and dv cc can be held high unintention- ally if the auxiliary adc inputs are greater than the forward bias on the internal esd protection diodes. for this reason, it is recommended that the auxiliary adc inputs return to 0 v when the part is placed in full power-down mode. in addition, all digital inputs on the ad7280a master device must return to 0 v when the part is placed in full power-down mode (see figure 37 ). however, if an external v drive supply is usedthat is, v drive is not connected to v reg then only the cnvst line must return low (see ). figure 38 when the ad7280a is placed into full power-down mode, the device must be left in full power-down for a minimum of 2 ms when the v reg and v ref pins are decoupled with 1 f capacitors. this ensures that the charge on the v reg and v ref decoupling capacitors dissipates sufficiently to allow the internal power-on reset circuit to activate when powering the ad7280a back up. this time is measured from the falling edge of the pd pin. shows a plot of the voltage on the v reg and v ref pins as the ad7280a is powering down with 1 f decoupling capacitors on the pins. shows a similar plot but with 10 f decoupling capacitors on the v reg and v ref pins. figure 18 figure 20 v ss ad7280a v reg 0.1f 10f 1f 0.1f 0.1f v dd v dd dv cc av cc 1f 0.1f v ref c ref alert sdo sclk sdi v drive master aux6 aux term aux5 aux4 aux3 aux2 aux1 10k ? must go to 0v in hardware power-down must go to 0v in hardware power-down cs pd cnvst dsp/micro- processor 09435-023 figure 37. v drive powered from v reg v ss ad7280a v reg 0.1f 10f 1f 0.1f 0.1f v dd v dd 10f 0.1f dv cc av cc 1f 0.1f v ref c ref alert sdo sclk sdi v drive master aux6 aux term aux5 aux4 aux3 aux2 aux1 10k ? must go to 0v in hardware power-down must go to 0v in hardware power-down cs pd cnvst dsp/micro- processor 2.7v to 5.5v supply 09435-024 figure 38. v drive powered from dsp/microprocessor
ad7280a rev. 0 | page 25 of 48 software power-down the ad7280a can be placed into software power-down mode, which requires 3.8 ma of current, by setting bit d8 in the control register through the serial interface. the cnvst pin should be gated out before generating a software power-down (see the cnvst control register section). when the ad7280a is powered down through the serial interface, the regulator, the reference, and the daisy-chain circuitry stay powered up, but the remaining analog and digital circuitry is powered down. this is necessary to ensure that the signal to power on the part, or the chain of parts, is correctly received. power-down timer the pd timer register allows the user to program a set time after which the ad7280a is automatically powered down. this timer functions as a time delay between the falling edge of the pd input (or the setting of bit d8 in the control register) and the ad7280a powering down. the pd timer can be set to a value from 0 minutes to 36.9 minutes, with a resolution of 71.5 sec. the user should first write to the pd timer register to define the desired delay. any subsequent falling edge on the pd input or setting of bit d8 in the control register starts the pd timer. when the programmed time elapses, the ad7280a checks the state of the pd pin. if the pd pin is low, the ad7280a powers down. if the pd pin is high, the part does not power down and continues to operate as normal. the default value of the pd timer register on power-up is 0x00. if the pd timer register is written to after the counter starts, the counter is reset to 0. the count then restarts automatically, without further input from the user, and counts to the new value in the pd timer register. if the new time in the pd timer register is 0, the part checks the state of the pd pin and powers down if the pd pin is low. note that when the pd timer is activatedfor example, by a falling edge on the pd pina subsequent rising edge on the pd pin does not disable the active pd timer. it is recommended that the pd pin be held low until an active pd timer expires. power-up time as described in the power-down section, a full power-down of the ad7280a (active low on the pd input) powers down all analog and digital circuitry. the recommended power-up time from hardware power-down, when the internal reference is decoupled with a 1 f capacitor, is 5.5 ms. it is recommended that no conversions be initiated until the 5.5 ms power-up time elapses because such conversions can result in inaccurate data. a software power-down powers down all analog and digital circuitry on the ad7280a except for the regulator, the 1.2 v band gap reference, and the daisy-chain circuitry. the recom- mended power-up time from software power-down, when the v ref pin is decoupled with a 1 f capacitor, is 1 ms. cell balancing outputs the ad7280a provides six cell balance outputs that can be used to drive the gate of external transistors as part of a cell balancing circuit. each cbx output can be set to provide either a 0 v or 5 v output with respect to the absolute amplitude of the negative terminal of the battery cell that is being balanced. for example, the cb6 output provides a 0 v or 5 v output with respect to the voltage on the vin5 analog input. the cbx outputs are set by writing to the cell balance register. the default value of the cell balance register on power-up is 0x00. vin6 cb6 vin5 cb5 vin4 cb4 vin3 cb3 vin2 cb2 vin1 cb1 vin0 ad7280a 10k? 10k? 10k? 10k? 10k? 10k? 09435-019 figure 39. cell balancing configuration as noted in the power-down timer section, a power-down timer can be programmed on the ad7280a. this timer can be used to allow cell balancing to occur for a set time before powering down the ad7280a. the power-down timer is independent of the cell balance timers. if no power-down timer is setthat is, if the pd timer register is at its default value of 0x00a falling edge on the pd pin switches off the cbx outputs and powers down the ad7280a. if a power-down timer is set, the cbx outputs are powered down when the programmed power-down timer elapses and the ad7280a is powered down. in an application with two or more ad7280a devices in a daisy chain, it is recommended that series resistors be placed between the cbx outputs of the ad7280a and the gates of the external cell balancing transistors. these resistors are recommended to protect the ad7280a in the event that the external cell balancing transistors are damaged during the initial connection of the monitoring circuitry to the battery stack. consideration should also be given to the protection of these external transistors during the initial connection of the monitoring circuitry to the battery stack.
ad7280a rev. 0 | page 26 of 48 an example of how damage to the external transistors can occur is a connection sequence that first provides the system ground (the ground supply to the master ad7280a in the daisy chain) followed by a connection from any of the battery cells at a potential high enough to exceed the v gs of the cell balancing transistor, for example 40 v. if these two connections are the first battery connections made in the system, the result is 40 v being applied to one of the vinx pins of the ad7280a through a series resistor. the 40 v battery connection is also directly applied to the source input of one of the cell balancing transistors. however, because no power has been supplied to the v dd pin of the ad7280a, all the cbx outputs are at 0 v. this results in a reverse voltage of 40 v across the v gs of the external transistor, which can damage the device. cell balance timers the ad7280a offers six cell balance timer registers that allow the on time of each cbx output to be programmed. the cbx timers can be set to a value from 0 minutes to 36.9 minutes. the resolution of the cbx timers is 71.5 sec. a value of 0x00 in a cbx timer register means that the timer is not activated. a non- zero value programmed to a cbx timer register configures the cbx timer for use, but the cbx outputs and the cbx timers are not activated until the cell balance register is written to. at the end of the individually programmed cbx time, the respective cbx output returns to its default state of 0 v output with respect to the absolute amplitude of the negative terminal of the battery cell that is being balanced. also at this time, the cell balance register is reset and the cbx timer registers continue to hold their programmed values. the default value of the cbx timer registers on power-up is 0x00. when using the cell balance timer feature, note that the timer on each cell balance output is operated from a single cb counter. when a nonzero value is programmed to any cbx timer register, this counter is activated by writing a nonzero value to the cell balance register. the current value of the counter is compared to the values programmed to each cbx timer register at 4.5 sec intervals (71.5 sec/16). when the value in the counter reaches the value in the cbx timer register, the cell balance output corresponding to that cbx timer register is switched off. note that the cell balance register has a higher priority than the cbx timer registers. a cbx output can be switched off by writing to the cell balance register even if the value programmed to the respective cbx timer register has not expired. writing a zero or a nonzero value to an active cbx timer register (corresponding cb output switched on) results in the cell balance counter being reset and automatically restarted. note that overwriting the cbx timer with 0 restarts the counter, but, because the timer value is now 0, the corresponding cb output is switched off. any write to a nonactive cbx timer register (corresponding cb output not switched on) has no effect on the cell balance counter. programming the cell balance timers it is recommended that the required cbx timer values be programmed to each individual cbx timer register before activating the cb counter. changing the cbx timer values while the counter is running is possible; however, writing to an active cbx timer register resets the counter, as described in the cell balance timers section. cell balance timer example 1 th e following sequence of steps programs a value of 214.5 sec to the cb1 and cb2 timer registers. 1. set bits[d4:d3] of the cb1 timer register and the cb2 timer register high. 2. set bits[d3:d2] of the cell balance register high. 3. wait 60 sec. 4. set bits[d4:d3] of the cb3 timer register high. 5. set bits[d4:d2] of the cell balance register high. in this example, the cb1 and cb2 outputs are switched on and the cell balance counter is activated. following the 60 sec wait, a value of 214.5 sec is written to the cb3 timer register, the cb3 output is switched on, and the on state of the cb1 and cb2 outputs is maintained. in this example, all three cb outputs are switched off at the same time (214.5 sec). this is because the cb counter was already active before the cb3 timer register was programmed and the cb3 output selected. cell balance timer example 2 in this example, follow the same sequence of steps described in the cell balance timer example 1 section, but increase the wait step from 60 sec to any value greater than 214.5 sec. the initial steps set up the cb1 and cb2 timers and activate the cb1 and cb2 outputs. however, because the wait state is now longer than the time programmed to the cb1 and cb2 timers, the cb1 and cb2 timers expire before the additional writes to configure cb3. the cb1 and cb2 outputs switch off, a 0 is written to bits[d3:d2] of the cell balance register, and the cb counter is reset to 0x00 before the commands to program the cb3 timer and to switch on the cb3 output are received. in this example, the second write to the cell balance registers which selects the cb1, cb2, and cb3 outputsis considered a new activation of the cb counter. the cb1, cb2, and cb3 outputs switch on and, if no further commands are written to the ad7280a, all three outputs switch off 214.5 sec after this second activation of the cb counter.
ad7280a rev. 0 | page 27 of 48 alert output t he alert output on the ad7280a can be used to indicate whether any of the following faults has occurred: ? cell overvoltage ? cell undervoltage ? auxiliary adc overvoltage ? auxiliary adc undervoltage following each completed conversion, the cell voltage and auxiliary adc measurement results are compared to the alert thresholds. the alert thresholds are set by writing to the cell overvoltage, cell undervoltage, aux adc overvoltage, and aux adc undervoltage registers. an alert output is generated if the cell voltage and/or the auxiliary adc results are outside the programmed alert thresholds. the alert output can be configured as a static or dynamic output by writing to the alert register. the static alert output is a high signal that is pulled low in the event of an overvoltage or under- voltage on the cell voltage or auxiliary adc input conversions. the dynamic alert is a square wave that can be programmed to a frequency of 100 hz, 1 khz, or 10 khz. the alert output can be used as part of a daisy chain, in which case the ad7280a at the top of the chain, that is, farthest away from the dsp/micro- processor, should be programmed to generate the initial alert output, and all other devices in the chain should be programmed to allow the alert signal to pass through. if a conversion result outside the programmed thresholds occurs, either on the device generating the initial alert signal or on any device in the chain, the alert signal is pulled low to indicate that an alert condition has occurred. at the end of the daisy chain, the master ad7280a, which is connected to the dsp/microprocessor, takes the alert signal from the chain and passes it in standard digital voltage format to the dsp/microprocessor. the configuration settings for the alert register are described in table 11 and table 12 . table 11. alert register settings, bits[d7:d4] 1 bits[d7:d6] bits[d5:d4] action 00 xx no alert signal generated or passed (default) 01 xx generates a static (high) alert signal to be passed down the daisy chain 10 00 generates a 100 hz square wave alert signal to be passed down the daisy chain 10 01 generates a 1 khz square wave alert signal to be passed down the daisy chain 10 10 generates a 10 khz square wave alert signal to be passed down the daisy chain 10 11 reserved 11 xx passes an alert signal from the ad7280a at higher potential in the daisy chain 1 x is dont care. table 12. alert register settings, bits[d3:d0] 1 bits[d3:d2] bits[d1:d0] action 00 xx includes all six voltage channels in alert detection (default) 01 xx removes vin5 from alert detection 10 xx removes vin5 and vin4 from alert detection 11 xx reserved xx 00 includes all aux adc channels selected for conversion in alert detection 2 (default) xx 01 removes aux5 from alert detection 3 xx 10 removes aux5 and aux3 from alert detection 3 xx 11 reserved 1 x is dont care. 2 includes six auxiliary adc channels in the alert detection if conversions on six auxiliary adc channels are selected in the control register; includes three auxiliary adc channels in the alert detection if conversions on three auxiliary adc channels are selected in the control register. 3 to remove aux5 or aux5 and aux3 from the alert detection, conversions on three auxiliary adc input channels only must be selected in the control register. some applications require fewer than six voltage measurements (see the connection of fewer than six voltage cells section). as shown in figure 35 , it is recommended that a channel that is not being used on the ad7280a be shorted to the channel below it. to prevent the incorrect triggering of the alert output in this application, the ad7280a allows the user to select up to two voltage channels that can be taken out of the overvoltage/ undervoltage detection circuit. this is programmed through bits[d3:d2] of the alert register. the user can also remove all or selected auxiliary adc channels from the detection circuit. this is programmed through bits[d1:d0] of the alert register in combination with bits[d15:d14] of the control register. the operation of the alert output can be verified by initiating a self-test conversion. the self-test conversion converts the band gap reference voltage, 1.2 v, which triggers an alert output if the cell undervoltage threshold is set higher than 1.2 v. to test the alert output, a self-test conversion should be initiated on the ad7280a farthest away from the dsp/microprocessor. the operation of the alert output can also be verified by increas- ing or decreasing the thresholds around a known input voltage to trigger an alert condition. the alert operation of each device in the daisy chain of ad7280as can be verified by, for example, decreasing the cell overvoltage threshold of that device below the value of the input voltage on the cells. initiating a conversion on all devices in the daisy chain pulls the alert signal low as it passes through that device. the relevant threshold on that device can then be returned to its previous value and the process repeated on the next device in the daisy chain.
ad7280a rev. 0 | page 28 of 48 register map table 13. register name register address register data read/write register cell voltage 1 0x00 d11 to d0 read only cell voltage 2 0x01 d11 to d0 read only cell voltage 3 0x02 d11 to d0 read only cell voltage 4 0x03 d11 to d0 read only cell voltage 5 0x04 d11 to d0 read only cell voltage 6 0x05 d11 to d0 read only aux adc 1 0x06 d11 to d0 read only aux adc 2 0x07 d11 to d0 read only aux adc 3 0x08 d11 to d0 read only aux adc 4 0x09 d11 to d0 read only aux adc 5 0x0a d11 to d0 read only aux adc 6 0x0b d11 to d0 read only self-test 0x0c d11 to d0 read only control 0x0d d15 to d8 read/write 0x0e d7 to d0 read/write cell overvoltage 0x0f d7 to d0 read/write cell undervoltage 0x10 d7 to d0 read/write aux adc overvoltage 0x11 d7 to d0 read/write aux adc undervoltage 0x12 d7 to d0 read/write alert 0x13 d7 to d0 read/write cell balance 0x14 d7 to d0 read/write cb1 timer 0x15 d7 to d0 read/write cb2 timer 0x16 d7 to d0 read/write cb3 timer 0x17 d7 to d0 read/write cb4 timer 0x18 d7 to d0 read/write cb5 timer 0x19 d7 to d0 read/write cb6 timer 0x1a d7 to d0 read/write pd timer 0x1b d7 to d0 read/write read 0x1c d7 to d0 read/write cnvst control 0x1d d7 to d0 read/write cell voltage registers the cell voltage registers store the conversion result from each cell input. the conversion result is in 12-bit straight binary format. auxiliary adc registers the aux adc registers store the conversion result from each auxiliary adc input. the conversion result is in 12-bit straight binary format. self-test register the self-test register stores the conversion result of the adc self-test. the conversion result is in 12-bit straight binary format. control register the control register is a 16-bit register that is used to configure the ad7280a. table 14 describes the operation of each bit in the control register. table 14. control register settings bits description [d15:d14] select conversion inputs 00 = six cell voltages and six aux adcs (default) 01 = six cell voltages and aux1, aux3, and aux5 10 = six cell voltages only 11 = adc self-test [d13:d12] read conversion results 00 = six voltages and six aux adcs (default) 01 = six voltages and aux1, aux3, and aux5 10 = six cell voltages only 11 = no-read operation d11 conversion start format 0 = falling edge of cnvst input (default) 1 = rising edge of cs [d10:d9] conversion averaging 00 = single conversion only (default) 01 = average by 2 10 = average by 4 11 = average by 8 d8 power-down format 0 = falling edge of pd input (default) 1 = software power-down d7 software reset 0 = take the ad7280a out of reset (default) 1 = reset the ad7280a [d6:d5] set acquisition time 00 = 400 ns (default) 01 = 800 ns 10 = 1.2 s 11 = 1.6 s d4 reserved; set to 1 d3 thermistor termination resistor 0 = function not in use (default) 1 = termination resistor connected d2 lock device address 0 = does not lock to new device address; continues to operate with device address 0x00 (default) 1 = part locks to new device address that it is presented with d1 increment device address 0 = does not increment the device address when transferring data up the daisy chain 1 = increments the device address when transferring data up th e daisy chain (default) d0 daisy-chain register readback 0 = function not in use; registers are read in single register readback mode 1 = set daisy chain for register readback (default)
ad7280a rev. 0 | page 29 of 48 select conversion inputs bits[d15:d14] of the control register determine which cell voltages and auxiliary adc inputs are converted following a convert start command. the default value of d15 and d14 on power-up is 00. read conversion results bits[d13:d12] of the control register determine which cell voltage and auxiliary adc conversion results are supplied to the serial or daisy-chain data output pins for readback. the default value of d13 and d12 on power-up is 00. conversion start format a conversion on the ad7280a ca n be initiated through the hardware cnvst pin or by issuing a software convert start command. bit d11 of the control register determines whether a conversion is initiated on the falling edge of the cnvst input or on the rising edge of the cs input. the default format on power-up is the cnvst pin, that is, 0. when using the rising edge of the cs input to initiate conversions, bit d11 is reset to 0 following the initiation of conversions. conversion averaging bits[d10:d9] of the control register determine the number of conversions completed on each input with the averaged results stored in the relevant result registers. the user can select a single conversion only or the average of two, four, or eight conversions. the default value of bits[d10:d9] on power-up is 00, that is, single conversion only. power-down format setting bit d8 of the control register places the ad7280a into software power-down. see the power-down section for more information. the default value of bit d8 on power-up is 0. software reset bit d7 of the control register allows the user to initiate a software reset of the ad7280a. two write commands are required to complete the reset operation. bit d7 must be set high to put the ad7280a into reset. bit d7 must then be set low to take the ad7280a out of reset. a software reset resets all user configurable registers to their default values with the exception of the lower byte of the control register (address 0x0e). when executing a software reset, care should be taken to ensure that bits[d6:d0] are not incorrectly overwritten. set acquisition time bits[d6:d5] of the control register determine the acquisition time of the adc. see the acquisition time section for more information. the default value of the acquisition time is 400 ns, that is, 00. thermistor termination resistor bit d3 of the control register should be set if the user wishes to use a single thermistor termination resistor on the aux term pin. note that, due to settling time requirements, the thermistor termination resistor option should only be used when the acqui- sition time of the ad7280a is set to its highest value, that is, 1.6 s (set bits[d6:d5] to 11). the default value of d3 is 0. lock device address bit d2 of the control register is used in conjunction with bit d1 to allow individual device a ddresses for each ad7280a in the daisy chain to be defined and locked to the part. bit d1 is used to generate the individual device addresses that are presented to each ad7280a in the daisy chain in the form of a write command. when bit d2 is set high, the ad7280a locks to the device address presented to it. this new device address is used for all subsequent crc calculations. when bit d2 is set low, the device address of the ad7280a is not locked. in this case, a device address of 0x00 is used for crc calculations. the default value of d2 is 0. increment device address bit d1 of the control register determines whether the ad7280a increments the device address that it receives as part of a write command when transferring that command up the daisy chain. when bit d1 is set to 1, the device address is incremented as the command is passed up the chain. this mode of operation is used on initial power-up and when coming out of a hardware power- down to allow individual device addresses for each ad7280a in the daisy-chain stack to be defined. when d1 is set low, no change is made to the device address as the command is passed up the chain. the default value of d1 is 1. daisy-chain register readback bit d0 of the control register enables the readback of individual registers from each ad7280a in a daisy chain. when bit d0 is set high, the application of sufficient clocks allows the data stored in the register address identified by the read register to be shifted out of each ad7280a in turn. this data is passed down the daisy chain and read back by the dsp/microprocessor. when bit d0 is set low, daisy-chain read is disabled. see the daisy-chain interface section and the examples of interfacing with the ad7280a section. the default value of d0 is 1. cell overvoltage register the cell overvoltage register determines the high voltage thresh- old of the ad7280a. cell voltage conversions that exceed the overvoltage threshold trigger the alert output. the ad7280a allows the user to set the overvoltage threshold to a value from 1 v to 5 v. the resolution of the overvoltage threshold is eight bits, that is, 16 mv. the default value of the overvoltage threshold on power-up is 0xff (5 v).
ad7280a rev. 0 | page 30 of 48 cell undervoltage register the cell undervoltage register determines the low voltage thresh- old of the ad7280a. cell voltage conversions lower than the undervoltage threshold trigger the alert output. the ad7280a allows the user to set the undervoltage threshold to a value from 1 v to 5 v. the resolution of the undervoltage threshold is eight bits, that is, 16 mv. the default value of the undervoltage threshold on power-up is 0x00 (1 v). aux adc overvoltage register the aux adc overvoltage register determines the high voltage threshold of the ad7280a auxiliary adc inputs. conversions that exceed this threshold trigger the alert output. the ad7280a allows the user to set the threshold to a value from 0 v to 5 v. the resolution is eight bits, that is, 19 mv. the default value of the auxiliary adc overvoltage threshold on power-up is 0xff (5 v). aux adc undervoltage register the aux adc undervoltage register determines the low voltage threshold of the ad7280a auxiliary adc inputs. conversions that are lower than this threshold trigger the alert output. the ad7280a allows the user to set the threshold to a value from 0 v to 5 v. the resolution is eight bits, that is, 19 mv. the default value of the aux adc undervoltage threshold on power-up is 0x00 (0 v). alert register t he alert register determines the configuration of the alert function. the alert can be configured as a static or dynamic signal. ? the static signal is a high signal that is pulled low to indicate that an overvoltage or undervoltage on a cell or on the auxiliary adc has occurred. ? the dynamic signal is a square wave, the frequency of which can be set to 100 hz, 1 khz, or 10 khz. when a number of ad7280as are operating in daisy-chain mode, the selection of static or dynamic alert is set on the ad7280a at the highest potential in the chain only. the alert registers on the remaining ad7280as in the chain should be programmed to pass the alert signal through the chain. each part passes the static or dynamic alert signal through the chain or pulls the signal low to indicate that an overvoltage or under- voltage on a cell or on the auxiliary adc has occurred. see table 11 and table 12 for more information about the alert register settings. the default value of the alert register on power-up is 0x00. cell balance register the cell balance register determines the status of the six cell balance outputs. the six cbx outputs are set by writing to bits[d7:d2] of the cell balance register. the cell balance register is reset by a software reset or following a hardware power-down. the default value of the cell balance register on power-up is 0x00. table 15. cell balance register settings bits description d7 set cb6 output 0 = output off 1 = output on d6 set cb5 output 0 = output off 1 = output on d5 set cb4 output 0 = output off 1 = output on d4 set cb3 output 0 = output off 1 = output on d3 set cb2 output 0 = output off 1 = output on d2 set cb1 output 0 = output off 1 = output on [d1:d0] reserved; set to 0 cbx timer registers the cbx timer registers allow the user to program individual times for each cell balance output. the ad7280a allows the user to set the cbx timer to a value from 0 minutes to 36.9 minutes. the resolution of the cbx timers is 71.5 sec. the default value of the cbx timer registers on power-up is 0x00. when the cbx timer value is set to 0x00, the cbx timer is not activated; that is, the cbx outputs are all controlled by the contents of the cell balance register only. for more information, see the cell balancing outputs section. table 16. cbx timer register settings bits description [d7:d3] 5-bit binary code to set the cb timer to a value from 0 minutes to 36.9 minutes [d2:d0] reserved; set to 000
ad7280a rev. 0 | page 31 of 48 pd timer register the pd timer register allows the user to configure a set time after which the ad7280a is automatically powered down. the ad7280a allows the user to set the pd timer to a value from 0 minutes to 36.9 minutes. the resolution of the pd timer is 71.5 sec. when using the pd timer in conjunction with the cbx timers, the value programmed to the pd timer should exceed that programmed to the cbx timer by at least 71.5 sec because the pd timer takes priority over the cbx timers. the default value of the pd timer register on power-up is 0x00. table 17. pd timer register settings bits description [d7:d3] 5-bit binary code to set the pd timer to a value from 0 minutes to 36.9 minutes [d2:d0] reserved; set to 000 read register the read register, in conjunction with bits[d13:d12] and bit d0 of the control register, defines the read operations of the ad7280a. to read back a single register from either a single ad7280a or from a chain of ad7280a devices, the desired register address should first be written to the read register. to read back a series of conversion results from either a single ad7280a or from a chain of ad7280a devices, an address of 0x00 should be written to the read register. the default value of the read register on power-up is 0x00. table 18. read register settings bits description [d7:d2] 6-bit binary address for the register to be read [d1:d0] reserved; set to 00 cnvst control register the cnvst control register allows the user to gate the input signal from the cnvst pin. bit d0 of the cnvst control register allows the user to hold the internal cnvst signal high regardless of any external noise or glitches on the cnvst pin. this setting can be used in noisy environments to prevent incorrect initiation of conversions. when using the rising edge of cs to perform a software convert start, it is recommended that the cnvst pin be gated out by setting bit d0 high (see the section). conversion start format bit d1 of the cnvst control register allows the user to open a window in the cnvst gate that allows a single cnvst pulse through. the window is closed automatically following a falling edge on the cnvst pin. to use this functionality, the user should write 10 to bits[d1:d0] of the cnvst control register immediately before each conversion start request. the default value of the cnvst control register on power-up is 0x00. table 19. cnvst control register settings bits [d7:d2] bit d1 bit d0 description 000000 0 0 cnvst input not gated (default). 000000 x 1 cnvst input gated. 000000 1 0 allow single cnvst pulse. additional cnvst pulses are gated.
ad7280a rev. 0 | page 32 of 48 serial interface the ad7280a serial interface is mode 1 spi compliant, that is, the clock polarity (cpol) is 0, and the clock phase (cpha) is 1. the interface consists of four signals: cs , sclk, sdi, and sdo. the sdi line is used to transfer data into the on-chip registers, and the sdo line is used to read the on-chip registers and conversion result registers. sclk is the serial clock input for the device; all data transfers, either on sdi or on sdo, take place with respect to sclk. data is clocked into the ad7280a on the sclk falling edge. data is clocked out of the ad7280a on the sclk rising edge. the cs input is used to frame the serial data being transferred to or from the device. the ad7280a allows 32-bit data transfer only and resets a counter on the rising edge of cs to ensure that the ad7280a is automatically resynchronized with the dsp/microprocessor on every falling edge of cs . individual 8-bit or 16-bit words can be used to assemble a 32-bit command, but a single 32-bit wide cs frame is required to correctly structure the assembly of the 32-bit command. the rising edge of cs can also be used to initiate the sequence of conversions by writing to the upper byte of the control register. shows the timing diagram for the serial interface of the ad7280a. see the section for more information about the daisy-chain interface. figure 2 daisy-chain interface writing to the ad7280a in a battery monitoring application, up to eight ad7280as can be daisy-chained to allow up to 48 individual li-ion cell voltages to be monitored. each write operation must, therefore, include a device address and a register address, in addition to the data to be written. an additional identifier bit is also required when addressing all ad7280as in the daisy chain. the ad7280a spi interface, in combination with the daisy-chain interface, allows any register in the stack of eight ad7280as to be updated using one 32-bit write cycle. the 32-bit write sequence is shown in table 20 . the ad7280a also requires an 8-bit crc to be included in each write command. device address the device address is a 5-bit address that allows each individual ad7280a in the battery monitoring stack to be uniquely identified. on initial power-up , each ad7280a is configured with a default address of 0x00. a simple sequence of commands allows each ad7280a to recognize its unique device address in the stack (see the initializing the ad7280a section). this device address can then be locked to the ad7280a and used in subsequent read and write commands. the device address is written to and read from the ad7280a stack in reverse order, that is, lsb first. register address the register map for the ad7280a is provided in table 13 . each register address is six bits long and is used when writing to or reading from the on-chip registers of the ad7280a. register data when issuing a write command to a part in the stack of ad7280a devices, the data to be written is an 8-bit word. as shown in table 13 , all read/write registers are eight bits wide. for more information about the correct settings for each register, see the register map section. address all parts the ad7280a allows write commands to be issued simultane- ously to all devices in the daisy chain, as well as write commands to individual ad7280as. a write to all devices in the daisy chain is completed by setting bit d12 of the write command to 1. when issuing a write all command, the device address should be set to 0x00. this device address is also used to calculate the 8-bit crc for transmission with the write all command. 8-bit crc the ad7280a includes an 8-bit cyclic redundancy check (crc) on all write commands to either individual devices or to a chain of devices. an ad7280a that receives an invalid crc in the write command does not execute the command. the crc on the write command is calculated based on bits[d31:d11] of the write command. these bits include the device address, the register address, the data to be written, the address all parts bit, and bit d11. for more information about the crc, see the cyclic redundancy check section. bit pattern (010) a required fixed bit pattern of 010 to bits[d2:d0] of the 32-bit write command of the ad7280a provides an additional stage of verification. the correct position of this bit pattern is verified on each write command received by the ad7280a. an ad7280a that receives an incorrect bit pattern in the write command does not execute the command. table 20. 32-bit write cycle device address 1 register address register data address all parts reserved (0 bit) 8-bit crc bit pattern (010) d31 to d27 d26 to d21 d20 to d13 d12 d11 d10 to d3 d2 to d0 1 the device address is configured lsb first. for example, to address the second device in the stack, that is, the first slave d evice, the sequence of bits input to the ad7280a should be 10000. the regist er address, data bi ts, and crc bits are input msb first.
ad7280a rev. 0 | page 33 of 48 reading from the ad7280a t here are two types of read operation for the ad7280a: ? conversion results read ? register data read the data returned from a conversion result read operation includes the device address, the channel address, the write acknowledge bit, and the 8-bit crc information, in addition to the 12 bits of conversion data. table 21 illustrates the 32-bit read cycle for a conversion result read. the data returned from a register data read operation includes the device address, the register address, the write acknowledge bit, and the 8-bit crc information, in addition to the eight bits of register data. table 22 illustrates the 32-bit read cycle for a register data read. the ad7280a spi interface, in combination with the daisy- chain interface, allows the conversion results of any ad7280a in a stack of eight ad7280as to be read back using an n 8 32-bit read cycle, where n is defined as the number of conver- sions completed on that part, that is, 12, 9, or 6 (see table 8 ). device address the device address is described in the writing to the ad7280a section. when reading back register or conversion data from the device using the daisy-chain readback mode, the sdi line must be set to write to a specific address. that is, the sdi line should not be allowed to idle high or low, and the address all parts bit must be set to 0. the address must be either the top part in the chain of ad7280a devices or an address with a value higher than that of the top part in the chain. writing to the highest available address (address 0x1f) and setting the address all parts bit to 0 is recommended. the 32-bit write command is 0xf800030a. channel address the channel address allows each individual voltage and auxil- iary adc input result to be uniquely identified. each channel address is four bits wide. the address for each channel is provided in the register map (see table 13 ). register address the register map for the ad7280a is provided in table 13 . each register address is six bits long and is used when writing to or reading from the on-chip registers of the ad7280a. register data the register data is the 8-bit register data that was requested in a previous write command. conversion data the conversion data is the 12-bit conversion result from the cell voltage inputs, the auxiliary adc inputs, or the adc self-test conversion. write acknowledge bit as described in the writing to the ad7280a section, an 8-bit crc is included in the write command transmitted to the ad7280a. the crc is calculated based on bits[d31:d11]. a crc check is completed before the write command is executed on the device. using the same crc algorithm, the ad7280a calculates the crc and compares it to the crc that was received by the part in the transmitted write command. if the two crc values match, the command is executed and the write acknowledge bit in the subsequent transmission of data from the device is set. if the transmitted and calculated crcs do not match, the write command is not executed, and the write acknowledge bit is set to 0. for examples of the use of the write acknowledge bit, see the wr ite ack nowledge section. 8-bit crc the ad7280a includes an 8-bit cyclic redundancy check (crc) on all data read back from the devi ce. when reading back conversion data from the ad7280a, the 8-bit crc includes the device address, the channel address, the conversion data, and the write acknowl- edge bit. when reading back register data from the ad7280a, the 8-bit crc includes the device address, the register address, the register data, two reserved zero bits, and the write acknowledge bit. in both cases, the crc is generated on bits[d31:d10] of the 32-bit read cycle and is transmitted using bits[d9:d2] of the same read cycle. for more information about the crc, see the cyclic redundancy check section. table 21. 32-bit read conversion result cycle device address 1 channel address conversion data write acknowledge 8-bit crc reserved (0 bits) d31 to d27 d26 to d23 d22 to d11 d10 d9 to d2 d1 to d0 1 the device address is configured lsb first. for example, to address the second device in the stack, that is, the first slave d evice, the sequence of bits input to the ad7280a should be 10000. the register ad dress, channel addr ess, data bits, and crc bits are input msb first. table 22. 32-bit read register data cycle device address 1 register address register data reserved (0 bits) write acknowledge 8-bit crc reserved (0 bits) d31 to d27 d26 to d21 d20 to d13 d12 to d11 d10 d9 to d2 d1 to d0 1 the device address is configured lsb first. for example, to address the second device in the stack, that is, the first slave d evice, the sequence of bits input to the ad7280a should be 10000. the regist er address, data bi ts, and crc bits are input msb first.
ad7280a rev. 0 | page 34 of 48 daisy-chain interface in a battery monitoring application, up to eight ad7280as can be daisy-chained together to allow up to 48 individual lithium ion cell voltages to be monitored. each ad7280a is capable of monitoring up to six li-ion cells and is powered from the top and bottom voltage of the six li-ion cells. as a result, the supply voltages of each ad7280a are offset by up to 30 v from adjacent ad7280as in the chain. for this reason, a standard serial interface daisy-chain method cannot be used. the ad7280a includes a daisy-chain interface separate from the standard spi interface. this daisy-chain interface allows each ad7280a in the chain to relay data to and from adjacent ad7280as. as described in the serial interface section, the spi interface consists of four signals: cs , sclk, sdi, and sdo. in addition to these pins, there are three optional interface pins: alert, cnvst , and pd . each of these seven interface signals is mirrored in the daisy-chain interface to allow communication between adjacent devices in a daisy chain. for example, the serial clock of each ad7280a is received on the sclk pin and passed to the device above it in the daisy chain using the sclkhi pin. the cs , sclk, sdi, cnvst , and pd pins, which pass data up the daisy chain, operate as 3 v or 5 v logic interface pins when the ad7280a is configured as a master device; these pins operate as daisy-chain interface pins when the ad7280a is configured as a slave device. the sdo and alert pins operate as 3 v or 5 v logic interface pins when the ad7280a is configured as a master device. these pins are tristated when the ad7280a is configured as a slave device. two additional pins, sdolo and alertlo, are required to pass data down the daisy chain. as described in the serial interface section, only one 32-bit write cycle is required to write to any register in a stack of eight ad7280as. the readback of conversion data from all channels monitoring the battery stack requires an n 8 32-bit read cycle, where n is defined as the number of conversions completed on that part, that is, 12, 9, or 6. the recommended sclk frequency to ensure correct operation of the daisy-chain interface is 1 mhz. with a 1 mhz sclk, it takes approximately 1.54 ms to read back the voltage conversions on 48 channels. when reading from a single device in a stack of ad7280a devices (daisy-chain register readback is disabled; bit d0 of the control register = 0), the sclk frequency must be lower than 1 mhz to read back the register data from parts up the chain of ad7280as. this is due to the propagation delay between adjacent parts in the daisy chain (see t delay in table 3 ). this delay does not apply if the part is reading registers or conversion data from the part in daisy-chain mode; that is, the maximum sclk of 1 mhz can always be used in daisy-chain mode. addressing the ad7280a while reading back conversion or register data an spi interface reads data and writes data at the same time: as the device is reading in one command, it provides output data on the sdo pin in the same read/write cycle. when reading both register and conversion data from the ad7280a using the daisy- chain readback mode, the sdi line must not idle high or low; it must be set up to address and write to either the top device used in the daisy chain or to a device with an address higher than the top device used in the daisy chain. in either case, the address all parts bit (bit d12 in the write command) should be set to 0, and a valid crc must be included. writing to the highest available address, that is, address 0x1f, and setting the address all parts bit to 0 is recommended. the 32-bit write command is 0xf800030a. initializing the ad7280a on initial power-up and when coming out of power-down, all ad7280as default to a device address of 0x00. the following sequence of commands should be followed to allow each ad7280a in the daisy chain to recognize its unique position in the chain. the following sequence allows device addresses on all parts in the chain to be configured and confirmed through daisy-chain readback. a subset of these commands can also be used to configure the device addresses without readback confirmation. 1. a single command should be sent to all devices in the chain to assert the lock device address bit (d2), to deassert the increment device address bit (d1), and to assert the daisy-chain register readback bit (d0). the 32-bit write command is 0x01c2b6e2. 2. a second command should be sent to all devices in the chain to write the address of the lower byte of the control register, 0x0e, to the read register on all devices. the 32-bit write command is 0x038716ca. 3. to verify that all ad7280as in the chain have received and locked their unique device address, a daisy-chain register read should be requested from all devices. this can be done by continuing to apply sets of 32 sclks framed by cs until the lower byte of the control register of each device in the daisy chain has been read back. the user should confirm that all device addresses are in sequence. the 32-bit write command is 0xf800030a. 4. this command should be repeated until the control register data has been read back from all devices in the daisy chain.
ad7280a rev. 0 | page 35 of 48 write acknowledge for all write commands received by the ad7280a, the device internally performs a crc calculation on bits[d31:d11] of the received data and verifies this crc against the crc transmitted by the dsp/microprocessor. if there is a difference between the crc generated internally and the crc received from the dsp/ microprocessor, the ad7280a does not perform the write oper- ation. the ad7280a also checks for the correct position of the bit pattern 010 in the write command, as described in the serial interface section. if there is a difference between the expected 010 pattern and the pattern received from the dsp/microprocessor, the ad7280a does not perform the write operation. if a subsequent 32 sclk cycle framed by a cs pulse is applied to the ad7280a, bit d10 (the write acknowledge bit) on sdo indicates to the processor whether the last write to the device was successful (the write acknowledge bit is set if the write was successful). the write acknowledge bit is included in the 8-bit crc on the read cycle. note that the read register must be loaded with any value other than 0x00 for the write acknowledge bit to be correctly passed down the chain of ad7280a devices. fo llowing is an example of how the write acknowledge bit can be used when writing to and configuring a stack of ad7280a devices. this example sets the high byte of the control register settings on all devices in a stack of eight ad7280as. 1. execute a write all command to load the read register with 0x0e (addresses the low byte of the control register). 2. execute a write all command to set the high byte of the control register (address 0x0d) to the desired values. 3. apply an additional eight sets of 32 sclks, each framed by cs , to the master device. the device address bits, d31 to d27, should be set to 0x1f for each 32 sclk frame. the 32-bit write command is 0xf800030a. the data read back from the master device on the first 32 sclk frame includes the write acknowledge bit for the control register high byte write to the master device. the data read back on the second 32 sclk frame includes the write acknowledge bit for the control register high byte write to the first slave device in the stack, and so on. to read back the write acknowledge bit from slave ad7280as in a daisy chain when single registers are being written to, bits[d13:d12] of the control register on lower devices in the chain must be set to 1 (a no-read operation on those devices). for example, to read back the write acknowledge bit from device 1 in the chain after writing to a register on that device, the read operation of device 0, the master device, must be turned off. also, the sclk frequency must be lower than 1 mhz when reading back the write acknowledge bit from devices higher in the chain than the master device in this mode. cyclic redundancy check the ad7280a 32-bit spi interface includes an 8-bit cyclic redundancy check (crc) on the read and write cycles. the crc can be used to detect alterations in the data during transmission to and from the ad7280a. the principle of a cyclic redundancy check is that the data to be transmitted is divided by a fixed poly- nomial. the remainder of this mathematical operation is then attached to the data and forms part of the transmission. at the receiving end, the same mathematical operation should be com- pleted on the data received. this operation confirms that the data received is the same as the data that was originally transmitted. the polynomial used by the ad7280a to calculate the crc bits is x 8 + x 5 + x 3 + x 2 + x + 1. this crc polynomial has a hamming distance of 4 for calculations up to 22 bits of data. the division is implemented using the digital circuit shown in figure 40 . write operation crc for writes to the ad7280a, the crc must be computed in the dsp/microprocessor and sent as part of the write command. the crc must be computed on bits[d31:d11] of the write command, that is, the device address, the register address, the data to be written, the address all parts bit, and bit d11, which is a reserved zero input bit. the data is divided by the crc polynomial, and the 8-bit remainder, following the division, becomes the crc bits, crc_7 to crc_0. if the user is addressing all parts in a stack of ad7280as (by asserting the address all parts bit, d12), the crc must be com- puted using a device address of 0x00, and the data written to the device must have a device address of 0x00. the ad7280a performs the same crc calculation on bits[d31:d11] of the received data, and it verifies this crc against the crc transmitted by the dsp/ microprocessor. if there is a difference between the crc gener- ated within the ad7280a and the crc received from the dsp/ microprocessor, the ad7280a does not perform the write opera- tion. to allow the user to verify that the command has been received and implemented by the ad7280as in the stack, a write acknowledge bit is also included in the 32-bit read cycles. for more information about the write acknowledge bit, see the wr ite ack nowle dge section. dq dq crc_0 data_in sclk dq crc_1 dq crc_2 dq crc_3 dq crc_4 dq crc_5 crc_6 crc_7 dq 09435-021 figure 40. crc implementation
ad7280a rev. 0 | page 36 of 48 read operation crc for reads from the ad7280a, the 8-bit crc is generated by the ad7280a based on bits[d31:d10] of the 32-bit read cycle and is transmitted using bits[d9:d2] of the same read cycle. the data received is divided by the crc polynomial, and the 8-bit remain- der, following the division, becomes the crc bits, crc_7 to crc_0. the user can compare the crc bits calculated with the crc that was received from the ad7280a to verify that there was no alteration in the data that was transmitted by the ad7280a. when operating in a daisy chain, each ad7280a receives conver- sion or register data from the device above it in the daisy chain and performs a crc calculation on the received data. if there is a difference between the crc generated internally and the crc received from the device above it in the daisy chain, the ad7280a replaces the received crc by an inversion of the internally gen- erated crc. crc pseudocode the following pseudocode can be used to calculate the crc. the following variables must first be declared: ? num_bits is the number of data bits used to calculate the crc result: 21 for a data write to the ad7280a, and 22 for a data read from the ad7280a. ? i is an integer variable. ? xor_1, xor_2, xor_3, xor_4, and xor_5 are integer variables. these outputs of the xor gates start with the leftmost xor gate in the circuit implementation (see figure 40). ? data_in represents the data bits that the crc is calculated on: bits[d31:d11] for a write operation, and bits[d31:d10] for a read operation. this data supplies the input to the first xor gate. ? crc_0, crc_1, crc_2, crc_3, crc_4, crc_5, crc_6, and crc_7 are integer variables. the outputs of the shift registers start at the leftmost shift register in the circuit implementation (see figure 40). with the exception of data_in, all variables should be initialized to 0. the following code implements the crc calculation as shown in figure 40. for (i=num_bits; i>=0; i--) { xor_5 = crc_4 ^ crc_7; xor_4 = crc_2 ^ crc_7; xor_3 = crc_1 ^ crc_7; xor_2 = crc_0 ^ crc_7; xor_1 = data_in[i] ^ crc_7; crc_7 = crc_6; crc_6 = crc_5; crc_5 = xor_5; crc_4 = crc_3; crc_3 = xor_4; crc_2 = xor_3; crc_1 = xor_2; crc_0 = xor_1; } crc calculation example 1 this example shows how a 32-bit write command, including the crc calculation, to the high byte of the control register on the master device (device 0) is assembled. the data to be written is 0x0c. the crc is computed in the dsp/microprocessor on bits[d31:d11], that is, the device address, the register address, the data to be written to the register, the address all parts bit, and the reserved bit. ? device address: 00000 (0x00) ? register address: 001101 (0x0d) ? data: 00001100 (0x0c) ? address all parts bit: 0 (0x0) ? reserved bit: 0 (0x0) the data input to the crc algorithm is, therefore, 000000011010000110000 (0x003430). following the completion of the calculation, the value of crc_7 to crc_0 is 01010001 (0x51). the data that is sent to the ad7280a for this serial write is, therefore, 0000 0001 1010 0001 1000 0010 1000 1010 (0x01a1828a). crc calculation example 2 this example shows how a 32-bit write command, including the crc calculation, to the high byte of the control register on device 1 in the daisy chain is assembled. the data to be written is 0x0c. the crc is computed in the dsp/microprocessor on bits[d31:d11], that is, the device address, the register address, the data to be written to the register, the address all parts bit, and the reserved bit. ? device address (written lsb first): 10000 (0x10) ? register address: 001101 (0x0d) ? data: 00001100 (0x0c) ? address all parts bit: 0 (0x0) ? reserved bit: 0 (0x0) the data input to the crc algorithm is, therefore, 100000011010000110000 (0x103430). following the completion of the calculation, the value of crc_7 to crc_0 is 01110100 (0x74). the data that is sent to the ad7280a for this serial write is, therefore, 1000 0001 1010 0001 1000 0011 1010 0010 (0x81a183a2).
ad7280a rev. 0 | page 37 of 48 crc calculation example 3 this example shows the breakdown of a 32-bit register read from the low byte of the control register of the master device, that is, device 0. the crc is computed in the ad7280a on bits[d31:d10], that is, the device address, the register address, the register data, two reserved zero bits, and the write acknowledge bit. the calculated crc is sent along with bits[d31:d10] and bits[d1:d0] to the dsp/microprocessor. t he data received from the ad7280a is as follows: 0000 0001 1100 0010 1000 0110 0110 1000 (0x01c28668). ? device address: 00000 (0x00) ? register address: 001110 (0x0e) ? register data: 00010100 (0x14) ? reserved 0s: 0 (0x0) ? write acknowledge: 1 (0x1) ? crc: 10011010 (0x9a) ? reserved 0s: 0 (0x0) the crc bits are computed again in the dsp/microprocessor on bits[d31:d10] of the data that is read back from the ad7280a. the data input to the crc algorithm is, therefore, 0000000111000010100001 (0x0070a1). following the completion of the calculation, the value of crc_7 to crc_0 is 10011010 (0x9a). this result matches the crc that was sent from the ad7280a; therefore, this transmission of data is valid. crc calculation example 4 this example shows the breakdown of a 32-bit conversion result read from the cell voltage 3 conversion result register of device 1. the crc is computed in the ad7280a on bits[d31:d10], that is, the device address, the channel address, the conversion data, and the write acknowledge bit. the calculated crc is sent along with bits[d31:d10] and bits[d1:d0] to the dsp/microprocessor. t he data received from the ad7280a is as follows: 1000 0001 0100 1100 1101 0101 0001 1000 (0x814cd518). ? device address (read lsb first): 10000 (0x10) ? channel address: 0010 (0x2) ? conversion data: 100110011010 (0x99a) ? write acknowledge: 1 (0x1) ? crc: 01000110 (0x46) ? reserved 0s: 0 (0x0) the crc bits are computed again in the dsp/microprocessor on bits[d31:d10] of the data that is read back from the ad7280a. the data input to the crc algorithm is, therefore, 1000000101001100110101 (0x205335). following the completion of the calculation, the value of crc_7 to crc_0 is 01000110 (0x46). this result matches the crc that was sent from the ad7280a; therefore, this transmission of data is valid.
ad7280a rev. 0 | page 38 of 48 examples of interfacing with the ad7280a t he ad7280a supports a number of read options. the user can read back the results from ? all conversions completed on all parts in the chain ? individual registers on all parts in the chain ? individual registers on selected parts in the chain in each case, the user must first write to the read register on the selected parts to configure that part to supply the correct data on the outputs. when reading back an individual register, the address of that register should be written to the read register of the selected part. when reading back conversion results from any or all parts in the chain, an address of 0x00 should be written to the read register of the selected parts. w hen the address written to the read register is 0x00, the conversion results selected for readback are controlled by setting bits[d13:d12] of the control register (see table 14 ). these bits allow the user to select one of four different read- back options: ? read back 12 conversion re sults: six voltage and six auxiliary. ? read back nine conversion results: six voltage and three auxiliary. ? read back six conversion results: six voltage results only. ? switch off the read operation on this part. t o read back an individual register from a single ad7280a in the daisy chain, follow these steps: 1. on all other parts in the chain, set bits[d13:d12] of the control register to 11 to select the no-read operation on those parts. 2. on the targeted part, set bits[d13:d12] of the control register to turn on the read operation. note that it is more efficient in terms of 32-bit write cycles to first switch off the read operation on all ad7280as in the daisy chain. this is achieved with a single write cycle, using bit d12 in the write command to address all parts in the chain. the user can then address the individual part and set bits[d13:d12] of the control register to turn on the read operation for that part. convert and readback routine when conversion data from any or all of the ad7280as in a daisy chain is read back, the conversion results returned from the ad7280a are the last completed set of conversions on that part. it is recommended that the user also set bits[d15:d14] of the control register to select the number of conversions to be completed on each part and initiate the conversions through either the cnvst pin or the rising edge of cs as part of the read operation. in this way, the user can implement a simple convert and readback routine with the most efficient number of 32-bit write and read operations. a general example of this routine, which converts and reads back from all parts in the ad7280a daisy chain, is as follows: 1. write 0x00 to the read register on all parts in the daisy chain. note that 0x00 is the default value of this register on power-up and following a software reset operation. 2. write to the control register on all parts. set bits[d15:d14] to select the required conversions. set bits[d13:d12] to select the required conversion results for readback. 3. initiate the conversions through either the falling edge of cnvst or the rising edge of cs (set bit d11 of the control register to select the conversion start format). 4. allow sufficient time for each conversion to be completed plus t wa i t . see the converting cell voltages and auxiliary adc inputs section. 5. apply a cs low pulse that frames 32 sclks for each conversion result to be read back. examples the following examples of conversion and/or readback routines can be used in an application that implements a chain of ad7280a devices to monitor the voltage and/or auxiliary adc inputs of the ad7280a on a stack of lithium ion batteries.
ad7280a rev. 0 | page 39 of 48 example 1: initialize all parts in a daisy chain on initial power-up and when coming out of power-down example 1 shows a typical device initialization routine. 1. to initialize all device addresses, set bit d2 and bit d0 of the control register to 1, and set bit d1 of the control register to 0 on all parts in the chain. the 32-bit write command is 0x01c2b6e2 (see table 23 , write 1). 2. write the register address corresponding to the lower byte of the control register to the read register on all parts. the 32-bit write command is 0x038716ca (see table 23 , write 2). 3. apply a cs low pulse that frames 32 sclks for each device in the chain to be read back. all conversion readbacks should simultaneously write the 32-bit command 0xf800030a, as described in the section (see , write 3). this read is used to verify that all ad7280as in the chain have received and locked their unique device addresses. confirm that all device addresses are in sequence. serial interface table 23 example 2: convert and read all parts, all voltages, and all auxiliary adc inputs in this example, it is assumed that all ad7280as in the daisy chain have been initialized to their correct device addresses. 1. write register address 0x00 to the read register on all parts. a device address of 0x00 is used when computing the crc for commands to write to all parts. the 32-bit write command is 0x38011ca (see tabl e 24 , write 1). note that 0x00 is the default value of the read register on power-up and after a software reset; therefore, this write operation may not be necessary. 2. set bits[d15:d12] of the control register to 0 on all parts. the 32-bit write command is 0x01a0131a (see table 24 , wr ite 2). note that this is the default value of bits[d15:d12] of the control register on power-up and after a software reset; therefore, this write operation may not be necessary. 3. program the cnvst control register to 0x02 on all parts to allow conversions to be initiated using the cnvst pin. the 32-bit write command is 0x03a0546a (see , wr ite 3). table 24 4. initiate conversions through the falling edge of cnvst . 5. allow sufficient time for all conversions to be completed plus t wa i t . following the completion of all conversions, apply a cs low pulse that frames 32 sclks for each conver- sion result to be read back. the 32-bit write command is 0xf800030a, as described in the section (see , write 4). serial interface table 24 table 23. example 1: initializing a ll ad7280a devices in a daisy chain write command device address register addre ss data write all d11 8-bit crc d2 to d0 32-bit write command write 1 00000 001110 00010101 1 0 11011100 010 0x01c2b6e2 write 2 00000 011100 00111000 1 0 11011001 010 0x038716ca write 3 11111 000000 00000000 0 0 01100001 010 0xf800030a table 24. example 2: converting and reading all voltages and all auxiliary adc inputs from all ad7280a devices write command device address register addre ss data write all d11 8-bit crc d2 to d0 32-bit write command write 1 00000 011100 00000000 1 0 00111001 010 0x038011ca write 2 00000 001101 00000000 1 0 01100011 010 0x01a0131a write 3 00000 011101 00000010 1 0 10000101 010 0x03a0546a write 4 11111 000000 00000000 0 0 01100001 010 0xf800030a
ad7280a rev. 0 | page 40 of 48 example 3: convert and read all parts, all voltages, and three auxiliary ad c inputs per part in this example, it is assumed that all ad7280as in the daisy chain have been initialized to their correct device addresses. 1. write register address 0x00 to the read register on all parts. a device address of 0x00 is used when computing the crc for commands to write to all parts. the 32-bit write command is 0x038011ca (see table 25 , write 1). note that 0x00 is the default value of the read register on power-up and after a software reset; therefore, this write operation may not be necessary. 2. set bit d15 and bit d13 of the control register to 0 on all parts. set bit d14 and bit d12 of the control register to 1 on all parts. the 32-bit write command is 0x01aa1062 (see table 25 , write 2). 3. program the cnvst control register to 0x02 on all parts to allow conversions to be initiated using the cnvst pin. the 32-bit write command is 0x03a0546a (see , wr ite 3). table 25 4. initiate conversions through the falling edge of cnvst . 5. allow sufficient time for all conversions to be completed plus t wa i t . following the completion of all conversions, apply a cs low pulse that frames 32 sclks for each conver- sion result to be read back. the 32-bit write command is 0xf800030a, as described in the section (see , write 4). serial interface table 25 table 25. example 3: converting and reading all voltages and three auxiliary adc inputs from all ad7280a devices write command device address register addre ss data write all d11 8-bit crc d2 to d0 32-bit write command write 1 00000 011100 00000000 1 0 00111001 010 0x038011ca write 2 00000 001101 01010000 1 0 00001100 010 0x01aa1062 write 3 00000 011101 00000010 1 0 10000101 010 0x03a0546a write 4 11111 000000 00000000 0 0 01100001 010 0xf800030a
ad7280a rev. 0 | page 41 of 48 example 4: convert and read a single voltage or auxiliary adc input result from one part in this example, it is assumed that all ad7280as in the daisy chain have been initialized to their correct device addresses. 1. the register address corresponding to the voltage or auxiliary adc input result to be read should be written to the read register of the part to be read (see table 13 for register addresses). in this example, the cell voltage 6 register result is read from device 3 in the stack. the 32-bit write command is 0xc382865a (see table 26 , write 1). 2. set bits[d13:d12] of the control register to 1 on all parts. this setting turns off the read operation on all parts. the 32-bit write command is 0x01b617ea (see table 26 , wr ite 2). 3. set bits[d13:d12] of the control register of the part to be read from such that the required voltage is read back. with the exception of a self-test conversion, it is not possible to convert on a single channel; six, nine, or 12 conversions must be completed. this example reads a voltage conversion from device 3 in the stack; therefore, bit d14 and bit d12 of the control register should be set to 0, and bit d15 and bit d13 should be set to 1 on device 3. the 32-bit write command is 0xc1b400fa (see table 26 , write 3). 4. program the cnvst control register to 0x02 on device 3 to allow conversions to be initiated using the cnvst pin on that part. the 32-bit write command is 0xc3a0417a (see , write 4). table 26 5. initiate conversions through the falling edge of cnvst . 6. allow sufficient time for all conversions to be completed plus t wa i t . 7. program the cnvst control register to gate the cnvst signal on all parts. the 32-bit write command is 0x03a0340a (see , write 5). this write prevents unintentional conversions from being initiated by noise or glitches on the table 26 cnvst pin. this write also updates the on- chip output registers of all devices in the daisy chain. 8. apply a cs low pulse that frames 32 sclks to read back the desired voltage or auxiliary adc result. this frame should simultaneously write the 32-bit command 0xf800030a, as described in the section (see , write 6). serial interface table 26 note that when reading from a single device in a stack of ad7280as, the sclk frequency must be lower than 1 mhz to read back the register data from parts higher in the chain than the master device. table 26. example 4: converting and reading a single vo ltage or auxiliary adc result from one ad7280a device write command device address register addre ss data write all d11 8-bit crc d2 to d0 32-bit write command write 1 11000 011100 00010100 0 0 11001011 010 0xc382865a write 2 00000 001101 10110000 1 0 11111101 010 0x01b617ea write 3 11000 001101 10100000 0 0 00011111 010 0xc1b400fa write 4 11000 011101 00000010 0 0 10000111 010 0xc3a0417a write 5 00000 011101 00000001 1 0 10000001 010 0x03a0340a write 6 11111 000000 00000000 0 0 01100001 010 0xf800030a
ad7280a rev. 0 | page 42 of 48 example 5: read a single configuration register on all parts in this example, it is assumed that all ad7280as in the daisy chain have been initialized to their correct device addresses. 1. set bit d0 of the control register to 1 on all parts. this write enables the daisy-chain register read operation on all parts. the 32-bit write command is 0x01c2b6e2 (see table 27 , wr ite 1). 2. the register address corresponding to the configuration register to be read should be written to the read register on all parts (see table 13 for register addresses). in this example, the cell balance register is read from all parts. the 32-bit write command is 0x038a12b2 (see table 27 , write 2). 3. apply a cs low pulse that frames 32 sclks for each device in the stack to read back the desired register contents from all parts. this frame should simultaneously write the 32-bit command 0xf800030a, as described in the section (see , write 3). serial interface table 27 example 6: read a single configuration register from one part in this example, it is assumed that all ad7280as in the daisy chain have been initialized to their correct device addresses. 1. set bits[d13:d12] of the control register to 1 on all parts. this setting turns off the read operation on all parts. the 32-bit write command is 0x01a6151a (see table 28 , write 1). 2. set bits[d13:d12] of the control register of the part to be read from to 0. in this example, device 1 in the stack is to be read from. the 32-bit write command is 0x81a00222 (see table 28 , write 2). 3. the register address corresponding to the configuration register to be read should be written to the read register of the part that is to be read (see table 13 for register addresses). this example reads the alert register from device 1 in the stack. the 32-bit write command is 0x8389800a (see table 28 , write 3). 4. apply a cs low pulse that frames 32 sclks to read back the desired register contents. this frame should simultan- eously write the 32-bit command 0xf800030a, as described in the section (see , write 4). when reading from a single device in a stack of ad7280as, the sclk frequency must be lower than 1 mhz to read back the register data from parts higher in the chain than the master device. serial interface table 28 table 27. example 5: reading a single config uration register from all ad7280a devices write command device address register addre ss data write all d11 8-bit crc d2 to d0 32-bit write command write 1 00000 001110 00010101 1 0 11011100 010 0x01c2b6e2 write 2 00000 011100 01010000 1 0 01010110 010 0x038a12b2 write 3 11111 000000 00000000 0 0 01100001 010 0xf800030a table 28. example 6: reading a single conf iguration register from one ad7280a device write command device address register addre ss data write all d11 8-bit crc d2 to d0 32-bit write command write 1 00000 001101 00110000 1 0 10100011 010 0x01a6151a write 2 10000 001101 00000000 0 0 01000100 010 0x81a00222 write 3 10000 011100 01001100 0 0 00000001 010 0x8389800a write 4 11111 000000 00000000 0 0 01100001 010 0xf800030a
ad7280a rev. 0 | page 43 of 48 example 7: self-test conversion on all parts example 7 shows a self-test conversion routine for all parts in a daisy chain. 1. to select the self-test conversion, set bits[d15:d14] of the control register to 1, and set bits[d13:d12] of the control register to 0 on all parts. the 32-bit write command is 0x01b81092 (see table 29 , write 1). 2. set bit d0 of the control register to 1 on all parts. this setting enables the daisy-chain register read operation on all parts. the 32-bit write command is 0x01c2b6e2 (see table 29 , write 2). 3. the register address corresponding to the self-test conversion should be written to the read register of all parts (see table 13 for register addresses). the 32-bit write command is 0x038617ca (see table 29 , write 3). 4. program the cnvst control register to 0x02 on all parts to allow conversions to be initiated using the cnvst pin. the 32-bit write command is 0x03a0546a (see , wr ite 4). table 29 5. initiate conversions through the falling edge of cnvst . 6. allow sufficient time for the self-test conversions to be completed plus t wa i t . 7. the cnvst control register should be programmed to gate the cnvst signal on all parts. the 32-bit write command is 0x03a0340a (see , write 5). this write prevents unintentional conversions from being initiated by noise or glitches on the table 29 cnvst pin. this write also updates the on-chip output registers of all devices in the daisy chain. 8. apply a cs low pulse that frames 32 sclks to read back the desired voltage. this frame should simultaneously write the 32-bit command 0xf800030a, as described in the section (see , write 6). serial interface table 29 example 8: software reset on all parts example 8 shows a software reset routine for all parts in a daisy chain. 1. set bit d7 of the control register to 1 on all parts to place the ad7280a into software reset. the 32-bit write command is 0x01d2b412 (see table 30 , write 1). 2. set bit d7 of the control register to 0 on all parts to take the ad7280a out of software reset. the 32-bit write command is 0x01c2b6e2 (see table 30 , write 2). table 29. example 7: self-test co nversion on all ad7280a devices write command device address register addre ss data write all d11 8-bit crc d2 to d0 32-bit write command write 1 00000 001101 11000000 1 0 00010010 010 0x01b81092 write 2 00000 001110 00010101 1 0 11011100 010 0x01c2b6e2 write 3 00000 011100 00110000 1 0 11111001 010 0x038617ca write 4 00000 011101 00000010 1 0 10000101 010 0x03a0546a write 5 00000 011101 00000001 1 0 10000001 010 0x03a0340a write 6 11111 000000 00000000 0 0 01100001 010 0xf800030a table 30. example 8: software reset for all ad7280a devices write command device address register addre ss data write all d11 8-bit crc d2 to d0 32-bit write command write 1 00000 001110 10010101 1 0 10000010 010 0x01d2b412 write 2 00000 001110 00010101 1 0 11011100 010 0x01c2b6e2
ad7280a rev. 0 | page 44 of 48 emc guidelines schematic and layout guidelines to optimize the performance of a chain of ad7280a devices under noisy conditionsfor example, when experiencing electromagnetic interferencethe following schematic and layout guidelines should be observed (see figure 29 ). 1. all ad7280a devices in a daisy chain should be physically located on a single printed circuit board (pcb). daisy- chain connections between pcbs are not recommended. individual pcbs can be used for separate daisy chains. in this case, however, communication between pcbs is via a communication protocol such as spi or can. 2. individual 22 pf capacitors should be placed on each daisy-chain connection. the capacitors should be terminated to either the v ss pin of the upper device or the v dd pin of the lower device, depending on the direction in which data is flowing in the daisy chain. the pd , cs , sclk, sdi, and cnvst daisy-chain connections pass data up the chain. the 22 pf capacitors on these pins should be terminated to the v ss pin of the upper device in the chain. the sdolo and alertlo daisy-chain connections pass data down the chain. the 22 pf capacitors on these pins should be terminated to the v dd pin of the lower device in the chain. 3. a direct, low impedance trace should connect the v dd pin of the lower device with the v ss pin of the upper device. the ad7280a daisy-chain connections operate at the v dd /v ss voltage of the adjacent ad7280as. ensuring a low imped- ance path between the supplies optimizes the performance of the daisy-chain communications. 4. the application pcb should have a minimum of four layers. the ad7280a daisy-chain connections should be routed on an inner layer of the pcb. 5. the ad7280a daisy-chain connections should be shielded above and below by a v ss supply plane connected to the v ss pin of the upper device in the chain. the shield should extend from the v ss and daisy-chain low pins of the upper device (pin 15, pin 17, and pin 21 to pin 28) to cover the daisy- chain high pins of the lower device (pin 42 to pin 48), as well as a low impedance trace to the v dd pin. this shield provides maximum protection to the daisy-chain connec- tions when operating in a noisy environment. 6. the ad7280a devices should be placed as close together as possible on the pcb to minimize the length of the daisy- chain connections. 7. to minimize noise reaching the v dd /v ss pins of the ad7280a, ferrite beads should be inserted into the v dd and v ss supply traces coming from the battery. these beads can be inserted into the pcb traces between the battery cell connection on the pcb and the individual supply pins. note that these ferrite beads can be replaced with a small value of resistance. the maximum value of resistance that can be used is 20 . a resistor should not be included on the v ss line to the master chip. instead, a direct connection should be made from the battery cell connector to the v ss pin. an alog devices, inc., also recommends the following: ? inclusion of a 100 nf capacitor across the six individual cells that are monitored by the ad7280a. this capacitor should be placed physically close to the battery cell connector on the pcb. ? correct termination of all unused pins on the device. more information about the correct termination of unused pins can be found in the pin configuration and function descriptions section. operation in a noisy environment when the ad7280a is operating in a noisy environmentfor example, when electromagnetic interference is experienced glitches can occur on the spi or daisy-chain inputs and outputs. to limit the effect that such glitches may have on the operation of the ad7280a, each daisy-chain input is passed through a filter before being applied internally within the device. the filter on the pd pin is 130 s wide (see the section for more information). the filter on the remaining daisy-chain inputs ( power-down cs , sclk, sdi, cnvst , sdihi, and alerthi) is 150 ns wide. glitches wider than these values on any of the pins can have an effect on the ad7280a, and care should be taken to ensure correct operation. glitches that occur on the sclk and cs pins can result in the ad7280a losing synchronization with the dsp/microprocessor. however, such a loss of synchronization affects only the 32-bit word during which the glitch occurred. the ad7280a interface is reset on the rising edge of cs to ensure that the part is resyn- chronized, as described in the section. serial interface glitches that occur on the sdi or sdohi pin can result in a change of state of any of the bits in the 32-bit words that are written to or read from the chain of ad7280as. in this event, the 8-bit crc received by the ad7280a or by the dsp/micro- processor should not match the crc that is calculated based on the 32-bit word that was transmitted. glitches that occur on the alerthi pin are observed on the alert signal when output from the master device. care should be taken when designing the alert response software or hard- ware to ensure that such glitches are treated appropriately in the system. glitches that occur on the cnvst pin may be interpreted as a conversion start request. if this occurs during a read operation, it can result in incorrect data be ing read back from the ad7280a.
ad7280a rev. 0 | page 45 of 48 if a second convert start signal is received by the ad7280a while the conversion results are being read back, the data being read back from the device, or chain of devices, can be corrupted. the corruption of data occurs at the point in which the second con- vert start signal is introduced. any data read back prior to the second convert start signal is correct, but data read back after the second convert start signal may be corrupted. note that the corruption of data is not limited to the conversion result. the device address, chan nel address, and crc data can also be corrupted. the cnvst control register should be used to gate the convert start signal. this prevents any glitches that occur on the cnvst pin from being applied directly to the internal circuitry of the ad7280a. software flowchart see figure 41 for a software flowchart of a suggested sequence of steps that should be considered when operating the ad7280a in a noisy environment. 09435-028 has the required number of conversions been completed? yes no wait at least 5.5ms for all devices to be fully powered up power up ad7280a chain of devices initialize device ids on all parts in the chain write to control register to return db1/db2 to default values program configuration registers as required initiate a conversion write to cnvst control register to allow a single cnvst pulse through read back the conversion results from all devices in the daisy-chain readback mode check integrity of chain initialization by reading back the low byte of the control register from all devices is the crc correct for all data frames read back? have any parts in the chain returned a result of all 0s from the control register? ok no not ok yes ignore respective 32-bit frame data validation complete no yes power down ad7280a chain of devices place chain in power-down mode and wait at least 2ms for capacitors on v reg and v ref to dissipate charge figure 41. suggested software flowchart when operating in a noisy environment
ad7280a rev. 0 | page 46 of 48 outline dimensions compliant to jedec standards ms-026-bbc top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc lead pitch 1.60 max 0.75 0.60 0.45 view a pin 1 0.20 0.09 1.45 1.40 1.35 0.08 coplanarity view a rotated 90 ccw seating plane 7 3.5 0 0.15 0.05 9.20 9.00 sq 8.80 7.20 7.00 sq 6.80 051706-a figure 42. 48-lead low profile quad flat package [lqfp] (st-48) dimensions shown in millimeters ordering guide model 1 , 2 temperature range package description package option AD7280ABSTZ ?40c to +105c 48-lead lqfp st-48 AD7280ABSTZ-rl ?40c to +105c 48-lead lqfp st-48 ad7280awbstz ?40c to +105c 48-lead lqfp st-48 ad7280awbstz-rl ?40c to +105c 48-lead lqfp st-48 1 z = rohs compliant part. 2 w = qualified for auto motive applications. automotive products the ad7280aw models are available with controlled manufacturing to support the quality and reliability requirements of automoti ve applications. note that these automotive models may have specifications that differ from the commercial models; therefore, desi gners should review the specifications section of this data sheet carefully. only the automotive grade products shown are available for use in automotive applications. contact your local analog devices account representative for specific product ordering information and to obtain the specific automotive reliability reports for these models.
ad7280a rev. 0 | page 47 of 48 notes
ad7280a rev. 0 | page 48 of 48 notes ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09435-0-4/11(0)

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